Abstract: Generative AI for chip design and EDA has received tremendous interests from both academia and industry recently. It touches everything that chip designers care about, from RTL to PPA to design productivity. It is everywhere, in all levels of design abstractions, verification, and recently analog, mixed-signal, and RF designs as well. It has also been used to tweak the overall design flow and hyper-parameter tuning, but not yet all at once, e.g., generative AI from design specification to layout/tapeout, in a correct-by-construction manner. In this talk, I will cover some recent research advancement and results in Generative AI for chip design/EDA and share my perspectives.
Refreshments and networking.
Refreshments and networking.
Format:
Each table has 1 discussion lead + 2~3 invited participants + audience
Roundtable themes:
Roundtable Theme 1: Data Challenges and Needs for AI-Driven Hardware Design
Discussion Lead: Callie Hao
Roundtable Theme 2: Simulation to Generation: What can Generative AI offer?
Discussion Lead: Tong Geng
Roundtable Theme 3: ML-Driven Hardware Design: Tools, Formats, and Best Practices
Discussion Lead: Amir Yazdanbakhsh
Roundtable Theme 4: Industry-Academic-Government Collaboration
Discussion Lead: Haoxing (Mark) Ren
Roundtable Theme 5: Hardware Acceleration for Generative AI Models
Discussion Lead: Michael Pellauer
Abstract: Generative Artificial Intelligence (Generative AI), Large Language Models (LLMs), and Machine Learning (ML) are rapidly transforming many aspects of AI hardware accelerators and System-on-Chips (SoCs). The high computational demands and characteristics of emerging AI/ML workloads are dramatically impacting the architecture, VLSI implementation, and circuit design tradeoffs of hardware accelerators. Furthermore, as we reach the end of Moore’s law, straightforward technology scaling offers limited opportunities for improved energy efficiency and performance. Instead, we must rely more on domain-specific architectural features and software/hardware design for AI model inferencing and training. In this talk, we will provide an overview of NVIDIA’s technology innovations, from circuits to software to the entire datacenter, needed to enable today’s latest supercomputers for GenAI. Next, we will highlight recent work from NVIDIA Research into energy-efficient deep learning inference acceleration, including optimized accelerator micro-architectures, SW/HW co-design for low-precision quantization, and LLM compression techniques. We also highlight recent testchips targeting Transformer neural network inference, including a recent 5nm deep learning inference accelerator testchip that achieves up to 95.6 TOPS/W and a low-power accelerator for always-on vision.
Refreshments and networking.