Journals

N. Chauhan, N. Bagga, S. Banchhor, C. Garg, A. Sharma, A. Datta, S. Dasgupta, and Anand Bulusu. "BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: An Analog perspective." Nanotechnology, Oct. 22, 2021.

N. Chauhan, N. Bagga, S. Banchhor, A. Datta, S. Dasgupta and B. Anand, "Negative to Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits," in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, DOI: 10.1109/TUFFC.2021.3116897.

N. Chauhan, C. Garg, A. Sharma, S. Banchhor, A. Doneria, S. Dasgupta, Anand Bulusu, "Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET," in IEEE Transactions on Electron Devices, vol. 68, no. 10, pp. 5298-5304, Oct. 2021, DOI: 10.1109/TED.2021.3105952.

N. Chauhan, C. Garg, S. Deng, A. I. Khan, S. Dasgupta, Anand Bulusu, and Kai Ni, "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET," in IEEE Electron Device Letters, vol. 42, no. 8, pp. 1160-1163, Aug. 2021, doi: 10.1109/LED.2021.3087335.

N. Chauhan, Om Prakash, Aniket Gupta, Hussam Amrouch, “Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology,” Microelectronics Journal, Volume 115, 2021, 105193, ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2021.105193.

S. Yadav, N. Chauhan, S. Tyagi, A. Sharma, S. Banchhor, R. Joshi, R. Pratap, and Anand Bulusu. "A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET." Semiconductor Science and Technology 36, no. 12 (2021): 125002.

S. Banchhor, N. Chauhan and B. Anand, “A Physical Insight into Zero-Temperature Coefficient with Self-Heating Effect in SOI FinFET,” in journal of Iopscience Semicond. Sci. Technol. 2020.

N. Bagga, N. Chauhan, S. Banchhor, D. Gupta and S. Dasgupta, “Demonstration of a novel tunnel FET with channel sandwiched by drain,” in Journal of Iopscience Semicond. Sci. Technol., vol. 35, no. 1, 015008.

N. Bagga, N. Chauhan, D. Gupta, and S. Dasgupta. "A novel twofold tunnel FET with reduced miller capacitance: proposal and investigation." IEEE Transactions on Electron Devices 66, no. 7 (2019): 3202-3208.

K. S. Johnson, N. Chauhan, A. Bulusu, S. Dasgupta, “Physical Cause and Impact of Negative Capacitance Effect in Ferroelectric P(VDF-TrFE) Gate Stack and Its Application to Landau Transistor,” (communicated in OJFFC).

S.Yadav, N. Chauhan, S. Banchhor, A. Sharma, R. Chawla, A. Bulusu "Through-silicon-via induced stress aware FinFET buffer sizing in 3D ICs" Accepted in SST IOP.