In-progress. Refer to helloctf.org for more information.
Designed combinational logic locking circuits using Stripped Functionality Logic Locking (SFLL-fault) and Random Logic Locking (RLL) schemes on four circuits of varying sizes for the CSAW competition.
Worked as a teaching assistant for the graduate course, Introduction to VLSI System Design, a class of 90 students. Conducted lectures on fabrication techniques, stick diagrams and Cadence Virtuoso and Calibre tool for FreePDK45 library. Guided students toward semester long project on 64 Bit SRAM. Made solutions and graded assignments.