NE courses at INI

Neuromorphic analog circuits are inspired by the structure, function and plasticity of biological neurons and networks. Their computational primitives are based on electronic properties of silicon devices. Neuromorphic architectures typically rely on collective computation in parallel networks. Adaptation, learning and memory are implemented locally within processing stages. Transistors are primarily operated in weak inversion (below threshold), where they exhibit exponential I-V characteristics and low currents.

These properties lead to the feasibility of high-density, low-power implementations of functions that are expensive in other paradigms. The high parallelism and connectivity of neuromorphic circuits permit structures with massive feedback and real-time processing networks for high-dimensional signals (e.g. images).

Application domains of neuromorphic circuits include detailed real-time simulations of biological neurons and neural networks and the development of efficient and powerful sensors.

NE1

NE1  covers devices in CMOS technology (MOS transistor sub- and super-threshold, floating-gate MOS transistor, phototransducers), static circuits (differential pair, current mirror, transconductance amplifiers, multipliers, power-law circuits, resistive networks, etc.), dynamic circuits (linear and nonlinear filters, adaptive circuits), systems (multineuron chips, silicon retinas and cochleas), and an introduction to multi-chip systems that are based on spike event communication.

The lectures are accompanied by weekly laboratory sessions on the characterization and circuit simulation of neuromorphic circuits ranging from elementary devices to systems.

NE2

NE1  is recommended for those who intend to take the spring semester course Neuromorphic Engineering II, also known as NE2. NE2 teaches additional circuits and the process of chip design, from conception, circuit simulation, and layout, using a set of inexpensive software tools, ending with a project which could be submitted as a mini-project for CMOS fabrication.