Neuromorphic Engineering Class Chip Designs

From 2020 onwards

We are using a new classchip whose design started as one of the NE2 class projects.

Before 2020 classchips

The previous chip (classchip2005rev2008) that we used for the fall semester Neuromorphic Engineering class has a variety of test circuits such as single transistors, differential pairs, a bump circuit, a spiking neuron and synapse, follower integrator and differentiator, and a hysteretic differentiator. This chip is fabricated in MOSIS AMIS 1.6u technology (2M 2P) using MOSIS scalable rules. Fabrication cost about $1000 for 5 bonded chips. A final lot of 20 chips were fabricated before MOSIS shut down this line for MPW use in 2008. The full design of this chip, classchip2005rev2008, is available below. We are using it now as we gradually wear out the previous design classchip2005rev1.

User guide

  • classchip2005rev1manual.pdf - the user guide for this chip - accurate except for minor changes, including inclusion of ESD protection on test transistor drains and sources. Note these ESD structures cab affect minimum measurable currents.

classchip2005rev2008 - currently used

classchip2005rev1 (older design, still being used in our class)

If you need some other format, please send mail to

This design has been evolved over many years, starting in Mead's lab at Caltech, then later by INI. Designers include Carver Mead, Mass Sivilotti, John Lazzaro, Mary Anne Maher, Misha Mahowald, Steve Deweerth, Chris Diorio, Paul Hasler, Shih-Chii Liu, Jorg Kramer, Tobi Delbruck, Giacomo Indiveri, and Elissabetta Chicca. This last revision was assembled by Sam Zahnd and the students in the 2001 design course and then later revised by Giacomo Indiveri to fix some problems and swap a couple of circuits.

Photoreceptor test chip

This test chip has many structures for testing phototransduction with discrete devices and photoreceptor circuits. The circuit diagram is provided in the exercise instructions.

cns182recep93 schematic as PDF

cns182recep93 layout as Tanner L-Edit layout file


We provide these designs as a contribution to the community. By using these design resources, you agree to the following terms: These designs are distributed under the terms of the GNU Public License ( - TOCGPL), with the following additions:

  1. You are responsible for any use of these resources that infringe on existing patents. (We are not aware of any such existing IP.)

  2. We have built these circuits on several chips and they function correctly, but chip design is a tricky business, so there is absolutely no warranty as to functionality of these circuits.

  3. Use of these resources on chips that result in publications or for use in courses on electronic design must cite our relevant publications and must acknowledge the Institute of Neuroinformatics .