Research

Research Areas

A. Classical transistors

Why? The Boltzmann limit restricts the sub-threshold swing of the thermionic transistor to 60 mV/dec which prevents the lowering of operational voltages. Furthermore, short-channel effects prevent dimensional scaling of the planar transistor in bulk semiconductors.

What? We employ new device designs using 2D materials as the channel to mitigate challenges in both dimensional and voltage scaling.

How? We fabricate and characterise sub-thermionic (SS<60 mV/dec) 2D transistors which can operate at < 0.5 V regime. We lay specific emphasis on contact, doping and dielectric engineering. We also develop physics-based models to understand the behavior of these transistors.

Fabricated dual-gated MoS2 transistor demonstrating steep sun-threshold slope (SS<60 mV/dec) and high field effect mobility.

Read more: contact engineering, dielectric engineering, doping, sub-thermionic transistors, US patent

(top) 1-L Mos2 resistive RAM demonstrating multiple resistive states (bottom) MoS2-based synaptic transistor mimics spike time-dependent plasticity

B. Neuromorphic devices

Why? AI/ML algorithms running on traditional von Neumann architecture result in large power consumption and latency owing to frequent data transactions between the separated logic and memory elements.

What? Neuromorphic devices that mimic the operation of neurons and synapses can drastically lower power consumption in artificial and spiking neural network (ANN/SNN) architectures.

How? We fabricate and characterise low-power, CMOS-compatible synaptic and memristive devices to be implemented in ANN/SNN architectures. We also simulate the effect of device characteristics on the system-level performance of these NNs.

Read more: Resistive RAM, synaptic device, BEOL RRAM

C. Quantum devices

Why? Twisted 2D heterostructures host several emergent quantum phenomena which can be leveraged to create the next generation of quantum memories.

What? We wish to study interfacial ferroelectricity in marginally twisted TMDCs which can be used as both FeFET-based traditional memory and synaptic memory for SNNs.

How? We shall fabricate and characterise anti-parallel stacked MoS2 and WSe2 and measure the incipient ferroelectric properties of these heterostructures.

Heterostructure of two 1-L MoS2 stacked at ~0-degree angle results in alternating AB/BA domains resulting in switchable ferroelectric polarisation as evidenced by a counter-clockwise hysteresis loop and repeatable switching characteristics.

Read more: ferroelectricity in twisted MoS2, twisted graphene

Funded Research Projects

  1. (PI) Tunable synaptic plasticity in MoS2 transistors for low-power spiking neural networks (SNNs), Funding Body: SRG, SERB, GoI, 2 years

  2. (PI) Heterogenous Integration of Neuromorphic Devices with 2D Semiconductors Funding Body: Seed Grant, IITH, 2 years

  3. (PI) Back-end-of-line (BEOL) compatible MoS2 devices, Funding Body: ASCENT, European Nanoelectronics Access, 2 years