Research Interests

I am interested in Human Computer Interaction (HCI), Machine Learning and Information Retrieval, Information Security and Assurance, Logic Synthesis, Biomedical devices, Artificial Intelligence, Low-power computing and Re-configurable logic design.

Research Area

My research area include algorithm design for logic synthesis, reversible computing and field programmable gate array (fpga) design.

Research Publication

I am working as a research assistant in the VLSI Research Lab (VRL), Department of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh.

Journal Publication (2)

[All PDF]

  1. Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md Hasan Babu, and Ashis Kumar Biswas. "A Fast FPGA-Based BCDAdder". Circuits, Systems, and Signal Processing, Springer, New York, United States, volume: 37, issue no. 10, pp. 4384-4408. Date of Publication: October, 2018. DOI: 10.1007/s00034-018-0770-3.

  2. Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md Hasan Babu and Ashis Kumar Biswas. Low-power and area effcient binary coded decimal adder design using a look up table-based eld programmable gate array." IET Circuits,Devices & Systems (United Kingdom) volume 10, issue no. 3 (2016): pp. 163-172. Date of Publication: 23 May 2016, INSPEC Accession Number: 15989320, DOI: 10.1049/iet-cds.2015.0213.


Conference Paper (10)

[ALL PDF]

  1. Mubin Ul Haque, Leonardo Horn Iwaya, and M. Ali Babar. 2020. "Challenges in Docker Development: A Large-scale Study Using Stack Overflow". In ESEM`20: ACM/IEEE International Symposium on Empirical Software Engineering and Measurement (ESEM) (ESEM '20), October 8-9, 2020, Bari, Italy. ACM, New York, NY, USA, 11 pages. https://doi.org/10.1145/3382494.3410693.

  2. Brishty, Maksuda Akhter, Md Rajeb Talukder, Fahim Shihab Shan, Sadia Afrin Mim, Mubin Ul Haque, and Zarrin Tasnim Sworna. "Efficient Design of a Reversible Sorting Circuit in Nanotechnology", in 2nd International Conference on Innovation in Engineering and Technology, 26 - 27 December, 2019, Dhaka, Bangladesh.

  3. Mubin Ul Haque, Zarrin Tasnim Sworna, Sadia Afrin, Fahim Shihab Shan "A Compact Quantum Cost-Efficient Design of a Reversible Binary Counter", in 5th International WIE Conference Electrical and Electronic Engineering (WIECON-ECE 2019), 15 - 16 November, 2019, Bengalore, India.

  4. Nafiz Hossain, Nowrin Hossain, Zarrin Tasnim Sworna and Mubin Ul Haque, "A Fast and Compact Binary to BCD Converter Circuit", in 5th International WIE Conference Electrical and Electronic Engineering (WIECON-ECE 2019) 15-16 November 2019 at Bangalore, India.

  5. Zarrin Tasnim Sworna, Mubin Ul Haque and D. M. Anisuzzaman "High-Speed and Area-Efficient LUT-Based BCD Multiplier Design", in 4th IEEE WIECON-ECE 2018 conference, 14 - 16 December, 2018, Pattaya, Thailand.

  6. Zarrin Tasnim Sworna, Mubin Ul Haque and Shahedur Rahman "An FPGA-Based Divider Circuit Using Simulated Annealing Algorithm", accepted in 18th International Symposium on Communications and Information Technologies (ISCIT 2018), 26-29 September, 2018, Bangkok, Thailand.

  7. Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md Hasan Babu, and Lafifa Jamal. ``A Cost-Efficient LUT-Based BCD Adder Design." In IEEE Future Technologies Conference (FTC) 2017, pp. 874-882. Technically Sponsored by IEEE, 29-30 November 2017, Vancouver, BC, Canada.

  8. Zarrin Tasnim Sworna, \textbf{Mubin Ul Haque}, Hafiz Md Hasan Babu, Lafifa Jamal, and Ashis Kumer Biswas. ``An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem." In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 116-121. IEEE, Bochum, Germany, July 3-5, 2017. DOI: 10.1109/ISVLSI.2017.292017.

  9. Zarrin Tasnim Sworna, Mubin Ul Haque, and Hafiz Md Hasan Babu. ``A LUT-based matrix multiplication using neural networks." In \emph{2016 IEEE International Symposium on Circuits and Systems (ISCAS)}, pp. 1982-1985. IEEE, Montreal, Canada, 22-25 May, 2016. DOI: 10.1109/ISCAS.2016.7538964.

  10. Mubin Ul Haque, Zarrin Tasnim Sworna, and Hafiz Md Hasan Babu. ``An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA." In \emph{2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)}, pp. 445-450. IEEE, Kolkata, India, 4-8 Jan. 2016. DOI: 10.1109/VLSID.2016.39.

Research Profile


Google Scholar Link: https://scholar.google.com/citations?user=zkXUCDUAAAAJ&hl=en

DBLP Link: https://dblp.org/pers/hd/h/Haque:Mubin_Ul

Research Gate Link: https://www.researchgate.net/profile/Mubin_Ul_Haque