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Principal Investigator: Prof. Yong Moon
Office: #1307, Hyungnam Memorial Engineering Building, Soongsil Univ
Email: moony@ssu.ac.kr
Professional Experience
Senior research engineer, LG Semicon co., Ltd. (1997 ~ 1999)
Professor, School of Electronic Engineering, Soongsil Univ (1999 ~ Present)
Education
Ph.D., Department of Electronic Engineering, Seoul National Univ, Seoul, Korea (1997)
M.S., Department of Electronic Engineering, Seoul National Univ, Seoul, Korea (1992)
B.S., Department of Electronic Engineering, Seoul National Univ, Seoul, Korea (1990)
Professional Experience
Senior Research Engineer, LG Semiconductors, 1997–1999
Chair, IEEE Solid-State Circuits Society (SSCS) Seoul Chapter, 2016–2018
Visiting Scholar, University of California, Santa Cruz, 2019–2020
Research Interest
PLL(Phase-Locked Loop), Data converter, Low-power circuit, Mixed signal IC, RF circuit
Graduates
Jae-Hyuk Choi (최재혁)
M.S. Candidate (Mar. 2024 ~ )
Education
B.S., Electronic Engineering, Soongsil Univ (Mar.2018 ~ Feb. 2024)
Research Interest
PLL(Phase-Locked Loop) design, SAR ADC
Ki-Yang Kim (김기양)
M.S. Candidate (Mar. 2025 ~ )
Education
B.S., Electronic Engineering, Hansung Univ (Mar.2019 ~ Feb. 2025)
Research Interest
PLL(Phase-Locked Loop) design, TDC
Sung-Mo Yoon (윤성모)
M.S. Candidate (Mar. 2025 ~ )
Education
B.S., Electronic Engineering, Hansung Univ (Mar.2019 ~ Feb. 2025)
Research Interest
PLL(Phase-Locked Loop) design, DCO
Jin-Sik Choi (최진식)
M.S. Candidate (Mar. 2025 ~ )
Education
B.S., Electronic Engineering, Hansung Univ (Mar.2019 ~ Feb. 2025)
Research Interest
PLL(Phase-Locked Loop) design, CDR
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