2024

1. [SRC'24] C. Shim and B. Kim, "Design of Efficient Integer/Floating-Point Digital Compute-in-Memory Macro for Edge/Cloud Deep Learning with Reconfigurable Computing Precisions and Compressed Digital Adders and Accumulators," SRC TECHCON, Sep. 2024 (accepted)

2. [TCAS-I'24] C. Yu, H. Jiang, J. Mu, K. Chai, T. Kim, and B. Kim, "A Dual 7T SRAM-Based Zero-Skipping Compute-In-Memory Macro with 1-6b Binary Searching ADCs for Processing Quantized Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers [PAPER]

3. [NICE'24] S. Bezugam, Y. Wu, J. Yoo, D. Strukov, and B. Kim, "Quantized Context Based LIF Neurons for Recurrent Spiking Neural Networks in 45nm," Neuro-Inspired Computational Elements Conference, Apr. 2024 [Arxiv]

4. [ISSCC'24] C. Shim, J. Bae, and B. Kim, “VIP-Sat: A Boolean Satisfiability Solver Featuring 5x12 Variable In-Memory Processing Elements with 98% Solvability for 50 Variables 218 Clauses 3-SAT Problems,” IEEE International Solid-State Circuits Conference, Feb. 2024 [PAPER]

5. [ISSCC'24] J. Bae, C. Shim, and B. Kim, “e-Chimera: A Scalable SRAM-based Ising Macro with Enhanced Chimera Topology for Solving Combinatorial Optimization Problems Within Memory,” IEEE International Solid-State Circuits Conference, Feb. 2024 [PAPER]

6. [ISSCC'24] J. Bae*, J. Koo*, C. Shim*, and B. Kim, “LISA: A 576x4 All-in-One Replica Spins Continuous-Time Latch-based Ising Computer Using Massively Parallel Random Number Generations and Replica Equalizations,” IEEE International Solid-State Circuits Conference, Feb. 2024 (*equal contribution) [PAPER]

7. [JSSC'24] J. Mu, C. Yu, T. Kim, and B. Kim, "Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2D/3D Partial Differential Equations," IEEE Journal of Solid-State Circuits, 2024 (Early Access) [PAPER]

8. [JSSC'24] Y. Su, T. Kim, and B. Kim, "FlexSpin: A CMOS Ising Machine with 256 Flexible Spin Processing Elements with 8b Coefficients for Solving Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits, 2024 (Early Access) [PAPER]

9. [JSSC'24] J. Bae*, W. Oh*, J. Koo, C. Yu, and B. Kim, "CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully-Parallel Spin Updates and Equalization of Spin States," IEEE Journal of Solid-State Circuits, Jan. 2024 (*equal contribution) [PAPER]

2023

1. [SSCL'23] Y. Su, T. Kim, and B. Kim, "A Reconfigurable CMOS Ising Machine with Three-Body Spin Interactions for Solving Boolean Satisfiability with Direct Mapping," IEEE Solid-State Circuits Letter, Aug. 2023 [PAPER]

2. [JSSC'23] C. Yu, J. Mu, Y.Su, K. Chai, T. Kim, and B. Kim, "A Time-Domain Wavefront Computing Accelerator with a 32×32 Reconfigurable PE Array," IEEE Journal of Solid-State Circuits, Aug. 2023 [PAPER]

3. [VLSI'23] J. Mu, C. Yu, T. Kim, and B. Kim, "A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations," Symposia on VLSI Technology and Circuits, Jun. 2023 [PAPER]

4. [ISCAS'23] Z. Wei, J. Mu, Y. Zheng, T. Kim, and B. Kim, "A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing," IEEE International Symposium on Circuits and Systems, May 2023 [PAPER]

5. [ISCAS'23] Q. Zang, W. Goh, L. Lu, C. Yu, J. Mu, T. Kim, B. Kim, A. Mani, and A. Do, "282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing," IEEE International Symposium on Circuits and Systems, May 2023 [PAPER]

6. [CICC'23] Y. Su, T. Kim, and B. Kim, "A Reconfigurable Ising Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions," IEEE Custom Integrated Circuits Conference, Apr. 2023 [Invited to SSCL Special Issue] [PAPER]

7. [CICC'23] C. Yu, J. Mu, K. Chai, T. Kim, and B. Kim, "A Continuous-Time Ising Machine Using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates," IEEE Custom Integrated Circuits Conference, Apr. 2023 [PAPER]

8. [TCAS-I'23] H. Kim, J. Mu, C. Yu, T. Kim, and B. Kim, "A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Apr. 2023 [PAPER]

9. [ISSCC'23] J. Bae*, W. Oh*, J. Koo, and B. Kim, "CTLE-Ising: A 1,440 Spins Continuous-Time Latch-based Ising Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States," IEEE International Solid-State Circuits Conference, Feb. 2023 (*equal contribution) [Invited to JSSC Special Issue] [PAPER]

10. [JSSC'23] J. Mu and B. Kim, "A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method," IEEE Journal of Solid-State Circuits, Feb. 2023 [PAPER]

11. [JSSC'23] F. Tu, Y. Wang, Z. Wu, L. Liang, Y. Ding, B. Kim, L. Liu, S. Wei, Y. Xie, and S. Yin, "ReDCIM: Reconfigurable Digital Computing-In-Memory Processor with Unified FP/INT Pipeline for Cloud AI Acceleration," IEEE Journal of Solid-State Circuits, Jan. 2023 [PAPER]

2022

1. [JSSC'22] C. Yu, T. Yoo, K. Chai, T. Kim, and B. Kim, "A 65nm 8T SRAM Compute-In-Memory Macro with Column ADCs for Processing Neural Networks," IEEE Journal of Solid-State Circuits, Nov. 2022 [PAPER]

2. [ESSCIRC'22] J. Mu, C. Yu, T. Kim, and B. Kim, "A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method," IEEE European Solid-State Circuits Conference, Sep. 2022 [PAPER]

3. [JSSC'22] Y. Su, H. Kim, and B. Kim, "CIM-Spin: A Scalable CMOS Annealing Processor with Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits, Jul. 2022 [PAPER]

4. [JETCAS'22] D. Kim, C. Yu, S. Xie, Y. Chen, J.-Y. Kim, B. Kim, J. Kulkarni, and T. Kim, "An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Jun. 2022 [PAPER]

5. [TCAS-I'22] J. Mu, H. Kim, and B. Kim, "SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Jun. 2022 [PAPER]

6. [JSSC'22] Y. Su, J. Mu, H. Kim, and B. Kim, "A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits, Mar. 2022 [Invited: CICC 2021 Special Issue]. [PAPER]

7. [ISSCC'22] Y. Su, T. Kim, and B. Kim, "FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems," IEEE International Solid-State Circuits Conference, Feb. 2022 [PAPER]

8. [ISSCC'22] F. Tu, Y. Wang, Z. Wu, L. Liang, Y. Ding, B. Kim, L. Liu, S. Wei, Y. Xie, and S. Yin, "A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise in-Memory Booth Multiplication for Cloud Deep Learning Acceleration," IEEE International Solid-State Circuits Conference, Feb. 2022 [PAPER]

2021

1. [ESSCIRC'21] C. Yu, K. Chai, T. Kim, and B. Kim, "A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC," IEEE European Solid-State Circuits Conference, Sep. 2021 [PAPER]

2. [JSSC'21] H. Kim, T. Yoo, T. Kim, and B. Kim, "Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks," IEEE Journal of Solid-State Circuits, Jul. 2021 [PAPER]

3. [VLSI'21] J. Mu, Y. Su, and B. Kim, "A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems," Symposia on VLSI Technology and Circuits, Jun. 2021 [PAPER]

4. [CICC'21] C. Yu, Y. Su, J. Lee, K. Chai, and B. Kim, "A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations," IEEE Custom Integrated Circuits Conference, Apr. 2021 [PAPER]

5. [CICC'21] Y. Su, J. Mu, H. Kim, and B. Kim, "A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems,"  IEEE Custom Integrated Circuits Conference, Apr. 2021 [Best Student Paper Candidate] [Invited to JSSC Special Issue] [PAPER]

6. [OJCAS'21] Y. Chen, L. Lu, B. Kim, and T. Kim, "A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications," IEEE Open Journal of Circuits and Systems, Feb. 2021 [PAPER]

7. [TCAS-I'21] C. Yu, T. Yoo, H. Kim, T. Kim, K. Chai, and B. Kim, "A Logic-Compatible eDRAM Compute-In-Memory with Embedded ADCs for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Feb. 2021 [PAPER]

8. [ISSCC'21] J. Mu and B. Kim, "A 21x21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method," IEEE International Solid-State Circuits Conference, Feb. 2021 [PAPER]

2020

1. [TVLSI'20] Y. Chen, L. Lu, B. Kim, and T. Kim, "Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory," IEEE Transactions on VLSI Systems, Dec. 2020 [PAPER]

2. [ISCAS'20] J. Mu and B. Kim, "A 65nm Logic-Compatible Embedded AND Flash Memory for In-Memory Computation of Artificial Neural Networks," IEEE International Symposium on Circuits & Systems, Oct. 2020 [PAPER]

3. [ISCAS'20] Y. Chen, L. Lu, B. Kim, and T. Kim, "Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing," IEEE International Symposium on Circuits & Systems, Oct. 2020 [PAPER]

4. [ISCAS'20] Q. Chen, Y. Liang, B. Kim, and C. Boon, "A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter," IEEE International Symposium on Circuits & Systems, Oct. 2020 [PAPER]

5. [ISOCC'20] C. Yu, T. Yoo, T. Kim, K. Chai, and B. Kim, "Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks," 17th International SoC Design Conference, Oct. 2020 [Invited: Special Session]

6. [DATE'20] Q. Chen, Y. Su, H. Kim, T. Yoo, T. Kim, and B. Kim, "A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length," Design, Automation and Test in Europe Conference, Mar. 2020 [PAPER]

7. [CICC'20] C. Yu*, T. Yoo*, T. Kim, K. Chai, and B. Kim, "A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC," IEEE Custom Integrated Circuits Conference, Mar. 2020 (*equal contribution) [PAPER]

8. [ISSCC'20] Y. Su*, H. Kim*, and B. Kim, "CIM-Spin: A 0.5-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems," IEEE International Solid-State Circuits Conference, Feb. 2020 (*equal contribution) [PAPER]

2019

1. [ASSCC'19] H. Kim, Q. Chen, and B. Kim, "A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC," IEEE Asian Solid-State Circuits Conference, Nov. 2019 [Presented at ISSCC'19 SRP] [PAPER]

2. [ISOCC'19] H. Kim, Q. Chen, T. Yoo, T. Kim and B. Kim, “A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks," 16th International SoC Design Conference, Oct. 2019 [Invited: Special Session]

3. [ESSCIRC'19] H. Kim, Q. Chen, T. Yoo, T. Kim and B. Kim, “A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation”, IEEE European Solid-State Circuits Conference, Sep. 2019 [PAPER]

4. [SOCC'19] B. Kim, "Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks," IEEE System-On-Chip Conference, Sep. 2019 [Invited: Special Session]

5. [ISLPED'19] T. Yoo, H. Kim, Q. Chen, T. Kim and B. Kim, “A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks”, ACM/IEEE International Symposium on Low Power Electronics and Design, Jul. 2019 [PAPER]

2011-2018

1. [IRPS'18] G. Park, B. Kim, M. Kim, V. Reddy and C. H. Kim, “All-Digital PLL Frequency and Phase Noise Degradation Measurements Using Simple On-Chip Monitoring Circuits”, IEEE International Reliability Physics Symposium, Mar. 2018 [Best Student Paper Nomination][Conference Highlight] [PAPER]

2. [JSSC'17] S. Kundu, B. Kim, C. H. Kim, "A 0.2-to-1.45GHz Subsampling Fractional-N Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Static Phase Offset Detection," IEEE Journal of Solid-State Circuits, Mar. 2017 [PAPER]

3. [ISSCC'16] S. Kundu, B. Kim, C. H. Kim, "A 0.2-1.45GHz Sub-sampling Fractional-N All-Digital MDLL with Zero-offset Aperture PD based Spur Cancellation and In-situ Timing Mismatch Detection," IEEE International Solid-State Circuits Conference, Feb. 2016 [PAPER]

4. [CICC'15] B. Kim, H. Kim, C. H. Kim, "An 8bit, 2.6ps Two-Step TDC in 65nm CMOS Employing a Switched Ring-Oscillator Based Time Amplifier," IEEE Custom Integrated Circuits Conference, Sep. 2015 [Best Student Paper Nomination, Intel/IBM/Catalyst Foundation Award, Invited to JSSC] [PAPER]

5. [CICC'15] S. Kundu, B. Kim, C. H. Kim, "Two-step Beat Frequency Quantizer Based ADC with Adaptive Reference Control for Low Swing Bio-potential Signals," IEEE Custom Integrated Circuits Conference, Sep. 2015 [PAPER]

6. [VLSI'15] B. Kim, S. Kundu, C. H. Kim, "A 0.4-1.6GHz Spur-Free Bang-Bang Digital PLL in 65nm with a D-Flip-Flop Based Frequency Subtractor Circuit," Symposium on VLSI Circuits, Jun. 2015 [PAPER]

7. [CICC'14] B. Kim, S. Kundu, S. Ko, C. H. Kim, “A VCO-based ADC with a Multi-Phase Noise-Shaping Beat Frequency Quantizer Achieving 43dB SNDR for 1mV Input Signal,” IEEE Custom Integrated Circuits Conference, Sep. 2014 [PAPER]

8. [CICC'14] Q. Tang, B. Kim, Y. Lao, K. K. Parhi, C. H. Kim, “True Random Number Generator Circuits Based on Single- and Multi-Phase Beat Frequency Detection,” IEEE Custom Integrated Circuits Conference, Sep. 2014 [PAPER]

9. [JSSC'14] B. Kim, W. Xu, C. H. Kim, “A Supply-Noise Sensitivity Tracking PLL in 32nm SOI Featuring a Deep Trench Capacitor Based Loop Filter,” IEEE Journal of Solid-State Circuits, Apr. 2014 [Invited] [PAPER]

10. [CICC'13] B. Kim, W. Xu, C. H. Kim, “A Fully-Digital Beat-Frequency Based ADC Achieving 39dB SNDR for a 1.6mVpp Input Signal,” IEEE Custom Integrated Circuits Conference, Sep. 2013 [PAPER]

11. [VLSI'13] B. Kim, W. Xu, C. H. Kim, “A 32nm, 0.9V Supply-Noise Sensitivity Tracking PLL for Improved Clock Data Compensation Featuring a Deep Trench Capacitor Based Loop Filter,” Symposium on VLSI Circuits, Jun. 2013 [ISLPED International Low Power Design Contest Winner, Invited to JSSC] [PAPER]

12. [ICCAD'12] P. Zhou, W. Choi, B. Kim, C. H. Kim, S. Sapatnekar, "Optimization of On-Chip Switched-Capacitor DC-DC Converters for High-Performance Applications," IEEE/ACM International Conference on Computer Aided Design, Nov. 2012

13. [JSSC'12] D. Jiao, B. Kim, C. H. Kim, "Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation," IEEE Journal of Solid-State Circuits, Oct. 2012 [PAPER]

14. [SRC'11] D. Jiao, B. Kim, C. H. Kim, "A Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation under Resonant Supply Noise," SRC TECHCON, Sep. 2011

-2010

1. [CICC'08] J. Shin, J. Park, B. Kim, J. Ryu, C. Kim, J. Kim, S. Yang, H. Kim, J. Kim, “A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer,” IEEE Custom Integrated Circuits Conference, Sep. 2008 [PAPER]

2. [IEEK'07] B. Kim, H. Jung, K. Lee, H. Park,“A Substrate Resistance and Guard-ring Modeling for Noise Analysis of Twin-well Non-epitaxial CMOS Substrate,” IEEK Journal 44th, SD 44th, pp 330-340, April 2007

3. [IEEK'05] J. Nam, B. Kim, H. Park “A UTMI Compatible USB2.0 Transceiver Chip Design,” IEEK Journal 42th, SD 5th, pp 31-38, May 2005