Junjie Mu Ph.D. 2018 - 2022 (NTU), Kim Group Alumni, PhD #2

Employment

Architecture Engineer, Huawei Technologies, Shanghai, China, Jul. 2024-

Post-doc, School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), 2022-2024

Awards & Honors

Women in Engineering, Science, and Technology Development Grant Award, 2023

Publications

1. [TCAS-I'24] C. Yu, H. Jiang, J. Mu, K. Chai, T. Kim, and B. Kim, "A Dual 7T SRAM-Based Zero-Skipping Compute-In-Memory Macro with 1-6b Binary Searching ADCs for Processing Quantized Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers (accepted)

2. [JSSC'24] J. Mu, C. Yu, T. Kim, and B. Kim, "Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2D/3D Partial Differential Equations," IEEE Journal of Solid-State Circuits, 2024 (Early Access) [PAPER]

3. [JSSC'23] C. Yu, J. Mu, Y.Su, K. Chai, T. Kim, and B. Kim, "A Time-Domain Wavefront Computing Accelerator with a 32×32 Reconfigurable PE Array," IEEE Journal of Solid-State Circuits, Aug. 2023 [PAPER]

4. [VLSI'23] J. Mu, C. Yu, T. Kim, and B. Kim, "A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations," Symposia on VLSI Technology and Circuits, Jun. 2023 [PAPER]

5. [ISCAS'23] Z. Wei, J. Mu, Y. Zheng, T. Kim, and B. Kim, "A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing," IEEE International Symposium on Circuits and Systems, May 2023 [PAPER]

6. [ISCAS'23] Q. Zang, W. Goh, L. Lu, C. Yu, J. Mu, T. Kim, B. Kim, A. Mani, and A. Do, "282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing," IEEE International Symposium on Circuits and Systems, May 2023 [PAPER]

7. [CICC'23] C. Yu, J. Mu, K. Chai, T. Kim, and B. Kim, "A Continuous-Time Ising Machine Using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates," IEEE Custom Integrated Circuits Conference, Apr. 2023 [PAPER]

8. [TCAS-I'23] H. Kim, J. Mu, C. Yu, T. Kim, and B. Kim, "A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Apr. 2023 [PAPER]

9. [JSSC'23] J. Mu and B. Kim, "A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method," IEEE Journal of Solid-State Circuits, Feb. 2023 [PAPER]

10. [ESSCIRC'22] J. Mu, C. Yu, T. Kim, and B. Kim, "A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method," IEEE European Solid-State Circuits Conference, Sep. 2022 [PAPER]

11. [TCAS-I'22] J. Mu, H. Kim, and B. Kim, "SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Jun. 2022 [PAPER]

12. [JSSC'22] Y. Su, J. Mu, H. Kim, and B. Kim, "A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits, Mar. 2022 [Invited: CICC 2021 Special Issue]. [PAPER]

13. [VLSI'21] J. Mu, Y. Su, and B. Kim, "A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems," Symposia on VLSI Technology and Circuits, Jun. 2021 [PAPER]

14. [CICC'21] Y. Su, J. Mu, H. Kim, and B. Kim, "A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems,"  IEEE Custom Integrated Circuits Conference, Apr. 2021 [Best Student Paper Candidate] [Invited to JSSC Special Issue] [PAPER]

15. [ISSCC'21] J. Mu and B. Kim, "A 21x21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method," IEEE International Solid-State Circuits Conference, Feb. 2021 [PAPER]

16. [ISCAS'20] J. Mu and B. Kim, "A 65nm Logic-Compatible Embedded AND Flash Memory for In-Memory Computation of Artificial Neural Networks," IEEE International Symposium on Circuits & Systems, Oct. 2020 [PAPER]