Hyunjoon Kim Ph.D. 2018 - 2022 (NTU), Kim Group Alumni, PhD #1

Employment

Staff Engineer, Technology Innovation Directorate (TID) - ASIC Group, SLAC National Accelerator Laboratory, DOE at Stanford University, 2022-

Awards & Honors

IEEE ISSCC Student Travel Grant Award, 2019 (for his presentation at ISSCC 2020 Student Research Preview)

Publications

1. [TCAS-I'23] H. Kim, J. Mu, C. Yu, T. Kim, and B. Kim, "A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Apr. 2023 [PAPER]

2. [JSSC'22] Y. Su, H. Kim, and B. Kim, "CIM-Spin: A Scalable CMOS Annealing Processor with Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits, Jul. 2022 [PAPER]

3. [TCAS-I'22] J. Mu, H. Kim, and B. Kim, "SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Jun. 2022 [PAPER]

4. [JSSC'22] Y. Su, J. Mu, H. Kim, and B. Kim, "A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits, Mar. 2022 [Invited: CICC 2021 Special Issue]. [PAPER]

5. [JSSC'21] H. Kim, T. Yoo, T. Kim, and B. Kim, "Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks," IEEE Journal of Solid-State Circuits, Jul. 2021 [PAPER]

6. [CICC'21] Y. Su, J. Mu, H. Kim, and B. Kim, "A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems,"  IEEE Custom Integrated Circuits Conference, Apr. 2021 [Best Student Paper Candidate] [Invited to JSSC Special Issue] [PAPER]

7. [TCAS-I'21] C. Yu, T. Yoo, H. Kim, T. Kim, K. Chai, and B. Kim, "A Logic-Compatible eDRAM Compute-In-Memory with Embedded ADCs for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Feb. 2021 [PAPER]

8. [DATE'20] Q. Chen, Y. Su, H. Kim, T. Yoo, T. Kim, and B. Kim, "A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length," Design, Automation and Test in Europe Conference, Mar. 2020 [PAPER]

9. [ISSCC'20] Y. Su*, H. Kim*, and B. Kim, "CIM-Spin: A 0.5-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems," IEEE International Solid-State Circuits Conference, Feb. 2020 (*equal contribution) [PAPER]

10. [ASSCC'19] H. Kim, Q. Chen, and B. Kim, "A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC," IEEE Asian Solid-State Circuits Conference, Nov. 2019 [Presented at ISSCC'19 SRP] [PAPER]

11. [ISOCC'19] H. Kim, Q. Chen, T. Yoo, T. Kim, and B. Kim, “A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks," 16th International SoC Design Conference, Oct. 2019 [Invited: Special Session]

12. [ESSCIRC'19] H. Kim, Q. Chen, T. Yoo, T. Kim, and B. Kim, “A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation”, IEEE European Solid-State Circuits Conference, Sep. 2019 [PAPER]

13. [ISLPED'19] T. Yoo, H. Kim, Q. Chen, T. Kim, and B. Kim, “A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks”, ACM/IEEE International Symposium on Low Power Electronics and Design, Jul. 2019 [PAPER]