Chengshuo Yu Ph.D. 2019 - 2024 (NTU), Kim Group Alumni, PhD #4

Employment

Research Staff, Zhangjiang Lab, Chinese Academy of Science, China, May. 2024-

Awards & Honors

IEEE Solid-State Circuits Society (SSCS) Pre-Doctoral Achievement Award, 2023

Publications

1. [TCAS-I'24] C. Yu, H. Jiang, J. Mu, K. Chai, T. Kim, and B. Kim, "A Dual 7T SRAM-Based Zero-Skipping Compute-In-Memory Macro with 1-6b Binary Searching ADCs for Processing Quantized Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers [PAPER]

2. [JSSC'24] J. Mu, C. Yu, T. Kim, and B. Kim, "Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2D/3D Partial Differential Equations," IEEE Journal of Solid-State Circuits, 2024 (Early Access) [PAPER]

3. [JSSC'24] J. Bae*, W. Oh*, J. Koo, C. Yu, and B. Kim, "CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully-Parallel Spin Updates and Equalization of Spin States," IEEE Journal of Solid-State Circuits, Jan. 2024 (*equal contribution) [PAPER]

4. [JSSC'23] C. Yu, J. Mu, Y.Su, K. Chai, T. Kim, and B. Kim, "A Time-Domain Wavefront Computing Accelerator with a 32×32 Reconfigurable PE Array," IEEE Journal of Solid-State Circuits, 2023 [PAPER]

5. [VLSI'23] J. Mu, C. Yu, T. Kim, and B. Kim, "A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations," Symposia on VLSI Technology and Circuits, Jun. 2023 [PAPER]

6. [ISCAS'23] Q. Zang, W. Goh, L. Lu, C. Yu, J. Mu, T. Kim, B. Kim, A. Mani, and A. Do, "282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing," IEEE International Symposium on Circuits and Systems, May 2023 [PAPER] 

7. [CICC'23] C. Yu, J. Mu, K. Chai, T. Kim, and B. Kim, "A Continuous-Time Ising Machine Using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates," IEEE Custom Integrated Circuits Conference, Apr. 2023 [PAPER]

8. [TCAS-I'23] H. Kim, J. Mu, C. Yu, T. Kim, and B. Kim, "A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Apr. 2023 [PAPER]

9. [JSSC'22] C. Yu, T. Yoo, K. Chai, T. Kim, and B. Kim, "A 65nm 8T SRAM Compute-In-Memory Macro with Column ADCs for Processing Neural Networks," IEEE Journal of Solid-State Circuits, Nov. 2022 [PAPER]

10. [ESSCIRC'22] J. Mu, C. Yu, T. Kim, and B. Kim, "A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method," IEEE European Solid-State Circuits Conference, Sep. 2022 [PAPER]

11. [JETCAS'22] D. Kim, C. Yu, S. Xie, Y. Chen, J.-Y. Kim, B. Kim, J. Kulkarni, and T. Kim, "An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Jun. 2022 [PAPER]

12. [ESSCIRC'21] C. Yu, K. Chai, T. Kim, and B. Kim, "A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC," IEEE European Solid-State Circuits Conference, Sep. 2021 [PAPER]

13. [CICC'21] C. Yu, Y. Su, J. Lee, K. Chai, and B. Kim, "A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations," IEEE Custom Integrated Circuits Conference, Apr. 2021 [PAPER]

14. [TCAS-I'21] C. Yu, T. Yoo, H. Kim, T. Kim, K. Chai, and B. Kim, "A Logic-Compatible eDRAM Compute-In-Memory with Embedded ADCs for Processing Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, Feb. 2021 [PAPER]

15. [ISOCC'20] C. Yu, T. Yoo, T. Kim, K. Chai, and B. Kim, "Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks," 17th International SoC Design Conference, Oct. 2020 [Invited: Special Session]

16. [CICC'20] C. Yu*, T. Yoo*, T. Kim, K. Chai, and B. Kim, "A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC," IEEE Custom Integrated Circuits Conference, Mar. 2020 (*equal contribution) [PAPER]