Mohit D. Ganeriwala

Journals

Mohit D. Ganeriwala, Daniel Luque-Jarava, Francisco Pasadas, Juan J. Palacios, Francisco G. Ruiz, Andres Godoy, and Enrique G. Marin. "Effect of grain boundaries on metal atom migration and electronic transport in 2D TMD-based resistive switches." Nanoscale (2025).
Aishwarya Singh, Mohit D. Ganeriwala, Radhika Joglekar, and Nihar R. Mohapatra. "A Scalable Physics-Based Compact Model for Terminal Charge, Intrinsic Capacitance and Drain Current in Nanosheet Field Effect Transistors." IEEE Journal of the Electron Devices Society (2025).
S. Cruces, Mohit D. Ganeriwala, J. Lee, L. Völkel, D. Braun, A. Grundmann, K. Ran, E. González Marín, H. Kalisch, M. Heuken, A. Vescan, J. Mayer, A. Godoy, A. Daus, and M. C. Lemme. "Volatile MoS2Memristors with Lateral Silver Ion Migration for Artificial Neuron Applications", Small Sci., 5: 2400523, (2024).
Prabhat Khedgarkar, Mohit D. Ganeriwala, and Pardeep Duhan. “Investigation of the origin of 1/f noise in advanced 22 nm FDSOI MOSFETs”, Appl. Phys. Lett. 2024, 125 (20), 203506.
Mohit D. Ganeriwala, Alejandro Toral-Ĺ opez, Estela Calaforra-Ayuso, Francisco Pasadas, Francisco G. Ruiz, Enrique G. Marin, Andres Godoy. “Role of Point Defects and Ion Intercalation in Two-Dimensional Multilayer Transition Metal Dichalcogenide Memristors”, ACS Applied Nano Materials 2024, 7 (21), 24857-24865.
J. Cuesta-Lopez, Mohit D. Ganeriwala, E. G. Marin, A. Toral-Lopez, F. Pasadas, F. G. Ruiz, A. Godoy; “Numerical study of synaptic behavior in amorphous HfO2-based ferroelectric-like FETs generated by voltage-driven ion migration”. J. Appl. Phys. 2024, 136 (12), 124501.
Mohit D. Ganeriwala, R. Motos-Espada, E.G. Marin, Juan Cuesta-Lopez, M.G. Palomo, Noel Rodríguez, F. Ruiz and A. Godoy, “A flexible laser induced graphene memristor with volatile switching for neuromorphic applications” ACS Applied Materials & Interfaces 2024, 16 (37), 49724-49732
Toral-Lopez, Alejandro, E. G. Marin, F. Pasadas, Mohit D. Ganeriwala, F. G. Ruiz, D. Jiménez, and A. Godoy. "Reconfigurable frequency multipliers based on graphene field-effect transistors." Discover Nano 18, no. 1 (2023): 123.
Mohit D. Ganeriwala, A. Singh, A. Dubey, R. Kaur and N. R. Mohapatra, "A Bottom-Up Scalable Compact Model for Quantum Confined Nanosheet FETs," in IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 380-387, Jan. 2022, doi: 10.1109/TED.2021.3130015.
Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin, and Nihar R. Mohapatra. “A Unified Compact Model for Electrostatics of III-V GAA Transistors with different Geometries”, Journal of Computational Electronics, Vol. 20, Issue 5, pp. 1676, 2021
Ghaffar, Abdul, Mohit D. Ganeriwala, Kenta Hongo, Ryo Maezono, and Nihar R. Mohapatra. "Insights into the Mechanical and Electrical Properties of a Metal–Phosphorene Interface: An Ab Initio Study with a Wide Range of Metals." ACS omega 6, no. 11 (2021): 7795-7803.
Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin, Nihar R. Mohapatra, “A Compact model for III-V Nanowire electrostatics including band non-parabolicty”, Journal of Computational Electronics, Vol. 18, Issue 4, pp. 1229, 2019. (https://doi.org/10.1007/s10825-019-01389-1)
Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin, Nihar R. Mohapatra, “A Compact Charge and Surface Potential Model for III-V Cylindrical Nanowire Transistors”, IEEE Transactions on Electro Devices (IEEE TED), Vol. 66, Issue 1, pp. 73, 2019. (10.1109/TED.2018.2866885)
Mohit D. Ganeriwala, Chandan Yadav, Francisco G Ruiz, Enrique G Marin and Nihar R. Mohapatra, “Modeling of Quantum Confinement and Capacitance in III-V Gate All Around 1D Transistors”, IEEE Transactions on Electron Devices (IEEE TED), Vol. 64, Issue 12, pp. 4889, 2017. (10.1109/TED.2017.2766693)
Chandan Yadav, Mohit D. Ganeriwala, Nihar R. Mohapatra, Amit Agarwal and Yogesh Singh Chauhan, “Compact Modeling of Gate Capacitance in III-V Channel Quadruple-Gate FETs”, IEEE Transactions on Nanotechnology (IEEE TNANO), Vol. 16, Issue 4, pp. 703, 2017. (10.1109/TNANO.2017.2709752)
Mohit D. Ganeriwala, Chandan Yadav, Nihar R. Mohapatra, Sourabh Khandelwal, Chenming Hu and Yogesh Singh Chauhan, “Modeling of charge and quantum capacitance in low effective mass III-V MOSFETs”, Journal of Electron Devices Society (IEEE JEDS), Vol. 4, Issue 6, pp. 396, 2016.(10.1109/JEDS.2016.2586116)
Nihar R. Mohapatra, Mohit D. Ganeriwala and Satya Siva Naresh, “Effect of pre-gate carbon implant on narrow width behavipr and performance of High-K metal gate nMOS transistors”, IEEE Transactions on electron Devices (IEEE TED), Vol. 63, Issue 7, pp. 2708, 2016. (10.1109/TED.2016.2570600)
Pardeep Duhan, Mohit D. Ganeriwala, V. Ramgopal Rao and Nihar R. Mohapatra, “Anomalous Width Dependence of Gate Current in High-K Metal Gate NMOS Transistors”, IEEE Electron Device Letters (IEEE EDL), Vol. 36, Issue 8, pp. 739, 2015.(10.1109/LED.2015.2440445)

Conferences

Aishwarya Singh, Mohit D. Ganeriwala, and Nihar Ranjan Mohapatra. "Physics-based Scalable Compact Model for Terminal Charge, Intrinsic Capacitance and Drain Current in Nanosheet FETs." In 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp. 1-3. IEEE, 2024.
Aishwarya Singh, Mohit D. Ganeriwala, Ramandeep Kaur, and Nihar R. Mohapatra. "A simplified approach to include confinement induced band structure changes into the NsFET compact model." In 2022 IEEE International Conference on Emerging Electronics (ICEE), pp. 1-5. IEEE, 2022.
Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin, Nihar R. Mohapatra, “Significance of L-valley charges and a method to include it in electrostatic model of III-V GAA FETs”, IEEE Electron Device Technology and Manufacturing (EDTM) Conference, Penang, Malaysia, March 15-18, 2020.
Sarathchandran GM, Mohit D. Ganeriwala and Nihar R. Mohapatra, “Capacitance and surface potential model for III-V Double-Gate MOSFETs”, International Symposium on Devices, Circuits and Systems (ISDCS), Hiroshima, Japan, March 6-8, 2019.
Mohit D. Ganeriwala, Enrique G. Marin, Francisco G. Ruiz and Nihar R. Mohapatra, “A compact charge and surface potential model for III-V Quadruple-Gate with square geometry”, 2019 IEEE International Conference on Modeling of Systems Circuits and Devices (MOS-AK India 2019), Hyderabad, India, February 25-27, 2019. This paper received the Silver Leaf Award.
Amratansh Gupta, Mohit D. Ganeriwala and Nihar R. Mohapatra, “A unified charge centroid model for silicon and low effective mass III-V channel double gate MOS Transistors”, 32nd International Conference on VLSI Design (VLSID), Delhi, India, January 4-8, 2019.
Mohit D. Ganeriwala, Sarathchandran GM., Nihar R. Mohapatra, “A simple charge and capacitance compact model for asymmetric III-V DGFETs using CCDA”, IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, December 16-19, 2018. This paper received the Best Manuscript Award.
Mohit D. Ganeriwala, Enrique G. Marin, Francisco G. Ruiz and Nihar R. Mohapatra, “Computationally efficient analytic charge model for III-V cylindrical nanowire transistors”, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon(EUROSOI-ULIS) 2018, Granada, Spain, March 2018.
Mohit D. Ganeriwala, Pardeep Duhan and Nihar R. Mohapatra, “Detailed analysis of carrier transport through multi-stack gate dielectrics of modern MOS transistors”, IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, December 27-30, 2016.

Talks

An Atomistic Study of Point and Extended Defect in Performance of 2D Materials based Memristors for Neuromorphic Computing, IHT, University of Stuttgart, Germany, 2025
The role of point and extended defects in 2D-materials based memristor for neuromorphic computing: An atomistic study, The chair of ELD, RWTH University, Aachen, Germany, 2025
2D Materials based Memristors : A DFT Study, AtomElix group, Universidad Autónoma de Madrid Spain, 2023
2D Materials Based Memristors for Neuromorphic Computing, The Group of Computer Architecture (AGRA), University of Bremen Germany, 2023
Compact Modeling Solutions for III-V Multi-Gate Transistors, Mori Lab, Osaka University, 2018
Compact Modeling Solutions for III-V Multi-Gate Transistors, University of Granada, Spain, 2018
Quantum Mechanics without Equations, IIT Gandhinagar, 2017

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