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RESEARCH AREAS:
FPGA-based power efficient hardware acceleration for High-Performance Computing (HPC), High-Level Synthesis (HLS) for FPGAs and automotive embedded systems, especially for Autonomous Vehicles (AVs) and Advanced Driver Assistance Systems (ADAS).
Development of large scale software systems using C/C++ for Electronic Design Automation (EDA), HPC and Embedded Systems.
FPGA-based system design for real-world applications in Automotive, Networking, DSP, etc.
Computer-Aided-Design (CAD) algorithms and tools for FPGAs and multi-FPGA systems.
Embedded System Design for Automotive Electronic Systems and Internet-of-Things (IoT)
RESEARCH INFRASTRUCTURE:
State-of-the-art FPGA boards from Xilinx and Intel, FPGA acceleration boards from Nallatech and Terasic.
State-of-the-art CAD tools for HLS and FPGA-based system design from Intel and Xilinx such as Intel SDK for OpenCL and Xilinx Vivado.
State-of-the-art CAD tools for compilation and simulation of VHDL and Verilog models from Mentor Graphics, Synopsys and Cadence. Embedded System Design tools from Mentor Graphics.
State-of-the-art Desktop and Server workstations, compilers, debuggers, and Computer-Aided Software Engineering (CASE) tools for the development of large scale software systems.
Research Support (monetary and/or in kind)
Research Support (monetary and/or in kind)
Research Team
Research Team
Former Students
Former Students
Masters of Applied Science (2022 – 2024)
Thesis Title: Hardware Acceleration of Iterative Closest Point Algorithm
Using DPC++
Masters of Applied Science (2022 – 2024)
Thesis Title: Hardware Acceleration of Web Servers using FPGA's
Masters of Applied Science (2021– 2023)
Thesis Title: A New Resource Efficient Multi-Puf Design
Doctoral (2020 – 2023)
Thesis Title: An Optimized M-term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic
Former Students
Former Students
Masters of Applied Science (2020 – 2022)
Thesis Title: Design Space Exploration of the Physical Design of 12 nm Low Power AI Processor
Masters of Applied Science (2021 – 2023)
Thesis Title: Rapid prototyping and functional verification of power efficient AI processors on FPGA
Masters of Applied Scienc (2018 – 2020)
Thesis Title: Hybrid PUF Design Using Bistable Ring PUF and Chaotic Network
Masters of Applied Science (2020 – 2022)
Thesis Title: FPGA-Based Hardware Acceleration of Canny Image Edge Detector using SYCL
Masters of Applied Science (2019 – 2021)
Thesis Title: Automated Generation and Integration of AUTOSAR RTE Configurations
Masters of Applied Science (2016 – 2019)
Thesis Title: 3-D LIDAR Point Cloud Processing Algorithms.
Masters of Applied Science (2019 – 2021)
Thesis Title: Landmark Identification Using GPU for Autonomous Unmanned Aerial Vehicle in GPS Denied Navigation
Humaira Naimi
Humaira Naimi
Masters of Applied Science (2019 – 2021)
Thesis Title: Traffic Sign and Light Detection using Deep learning for Automotive Applications
Masters of Applied Science (2017 – 2019)
Thesis Title: Automated Generation and Integration of Autosar ECU Configurations
Masters of Applied Science (2019)
Thesis Title: FPGA-Based Acceleration of Self-Organizing Map (SOM) Algorithm using High-Level Synthesis
Masters of Applied Science (2016 – 2017)
Thesis Title: FPGA Based Acceleration of Expectation Maximization Algorithm using High-Level Synthesis.
Masters of Applied Science (2015 – 2018)
Thesis Title: Acceleration of k-Nearest Neighbor and SRAD Algorithms using Intel FPGA SDK for OpenCL.
Masters of Applied Science (2015 – 2017)
Thesis Title: High-Level Synthesis and Evaluation of an Automotive Radar Signal Processing Algorithm for FPGAs.
Asmeen Kashif
Asmeen Kashif
Doctoral (2013 – 2017)
Thesis Title: Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architecture.
Current Position: CAD Tool Engineer at Huawei Technologies
Masters of Applied Science (2015 – 2017)
Thesis Title: Acceleration of Deep Learning on FPGA.
Masters of Applied Science (2013 – 2016)
Thesis Title: FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm using High-Level Synthesis.
Masters of Applied Science (2013 – 2015)
Thesis Title: High-Level Synthesis and Evaluation of Secure Hash Standards for FPGAs.
Masters of Applied Science (2013 – 2015)
Thesis Title: Experimental Evaluation of an NoC Synthesis Tool.
Postdoctoral (2012 – 2014)
Thesis Title: Hardware/Software Prototyping and Evaluation of Wireless Sensor Network Protocol.
Kunal Jetly
Kunal Jetly
Masters of Applied Science (2010 – 2013)
Thesis Title: Experimental Comparison of Store and Forward and Wormhole Noc Routers for FPGAs.
Masters of Applied Science (2010 – 2012)
Thesis Title: An Exploration of the Feasibility of FPGA implementation of Face Recognition using Eigenfaces.
Masters of Applied Science (2009 – 2012)
Thesis Title: Design Space Exploration of FPGA based NoC Routers.
Masters of Applied Science (2008 – 2010)
Thesis Title: A New Simplified Algorithm Suitable for Implementation in FPGA for Turbo Codes.
Masters of Applied Science (2007 – 2010)
Thesis Title: NoC Prototyping on FPGAs: Component Design, Architecture Implementation and Comparison.
Masters of Applied Science (2007 – 2009)
Thesis Title: Design and Evaluation of Parametizable NoC Router for FPGAs.
Masters of Applied Science (2009)
Thesis Title: Implementation and Evaluation of an NoC Architecture for FPGAs.
Doctoral (2008)
Thesis Title: FPGA Based NoC Architecture for Multispectral Image Processing.
Hongmei Zhong
Hongmei Zhong
Masters of Applied Science (2008)
Thesis Title: FPGA Implementation of QMF Filter Bank using CSD Number System.
Omar Alryahi
Omar Alryahi
Masters of Applied Science (2008)
Thesis Title: A CAD Tool for Synthesizing Variants of Altera NIOS II Soft Core Processors.
Masters of Applied Science (2007)
Thesis Title: FPGA Implementation of a Wireless Sensor Network.
Masters of Applied Science (2007)
Thesis Title: A Low-Cost Processor-Based Logic Emulation System using FPGAs.
Masters of Applied Science (2007)
Thesis Title: Software Profiling for an FPGA Based CPU Core.
Raymond Lee
Raymond Lee
Masters of Applied Science (2007)
Thesis Title: DNLMS-Based Adaptive Filters for Echo Cancellation.
Masters of Applied Science (2007)
Thesis Title: A CAD Tool for Design Space Exploration of Embedded CPU Cores for FPGAs.
Masters of Applied Science (2006)
Thesis Title: Hardware Design and CAD for Processor-Based Logic Emulation System.
Muqeeth Syed
Muqeeth Syed
Masters of Applied Science (2006)
Thesis Title: Architecture and CAD for Processor-Based Logic Emulation System.
Masters of Applied Science (2006)
Thesis Title: Blind Adaptive Equalization for QAM Signals: New Algorithms and FPGA Implementation.
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