Publications

Patent

• Khalid, M., & Rose, J. (2003). U.S. Patent No. 6,604,230. Washington, DC: U.S. Patent and Trademark Office. 

Journals

1. Thirumoorthi, M; Heidarpur, M; Mirhassani, M; Khalid, M, An Optimized M-term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022,February.

2. Thirumoorthi, M; Jovanovic, M; Mirhassani, M; Khalid, M, Design and Evaluation of a Hybrid Chaotic-Bistable RingPUF, IEEE Transactions on Very Large Scale Integration

Systems, 2021.

3. Kashif, Asmeen; Khalid, Mohammed, Latency-optimised 3D multi-FPGA system with serial optical interface,International Journal of Computer Aided Engineering and Technology, 14(4), 2021.

4. Weiying Zeng, Mohammed A. S. Khalid, Xiaoye Han, Jimi Tjong: A Study on Extreme Learning Machine for Gasoline Engine Torque Prediction, IEEE Access 8: 104762-104774 (2020) 

5. Asmeen Kashif, Mohammed A. S. Khalid: Experimental evaluation and comparison of latency-optimized optical and conventional multi-FPGA systems, Des. Autom. Embed. Syst. 24(2): 63-77 (2020) 

6. Zereen, S., Lal, S., Khalid, M. , & Chowdhury, S. (2018). An FPGA-based controller for a 77 GHz MEMS tri-mode automotive radar. Microprocessors and Microsystems, 58, 34-40.

7. Manokaran, J. P. R., & Khalid, M.  (2017). Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs. Microprocessors and Microsystems, 51, 134-141.

8. Qing Y. Tang, Mohammed A. S. Khalid: Acceleration of k-Means Algorithm Using Altera SDK for OpenCL, ACM Trans. Reconfigurable Technol. Syst. 10(1): 6:1-6:19 (2016) 

9. Zeng, W., Khalid, M. , & Chowdhury, S. (2016). In-vehicle networks outlook: Achievements and challenges. IEEE Communications Surveys & Tutorials, 18(3), 1552-1571.

10. Brugge, M., & Khalid, M.  (2014). A Parameterizable NoC Router for FPGAs. JCP, 9(3), 519-528.

11. Singh, B. K., Coulter, J., Sayani, M. A. G., Sami, S. M., Khalid, M., & Tepe, K. E. (2013). Survey on communication architectures for wind energy integration with the smart grid. International Journal of Environmental Studies, 70(5), 765-776.

12. Liao, J., Singh, B. K., Khalid, M. , & Tepe, K. E. (2013). FPGA based wireless sensor node with customizable event-driven architecture. EURASIP Journal on Embedded Systems, 2013(1), 5.

13. Zhang, L., Fresse, V., Khalid, M., Houzet, D., & Legrand, A. C. (2009). Evaluation and design space exploration of a Time-Division multiplexed NoC on FPGA for image analysis applications. EURASIP Journal on Embedded Systems, 2009(1), 542035.

14. Anderson, Ian, D., Khalid, Mohammed, “SCBuild:  A CAD Tool for Design Space Exploration of Embedded CPU Cores for FPGAs, IET Computers and Digital Techniques, 3(1), 24 – 32, 2009, January.

15. Khalid, M. , & Xu, Y. (2008). A fast and effective timing-driven placement tool for FPGAs. Journal of Circuits, Systems, and Computers, 17(04), 663-673.

16. Tong, J. G., & Khalid, M.  (2008). Profiling Tools for FPGA-Based Embedded Systems: Survey and Quantitative Comparison. JCP, 3(6), 1-14.

17. Banović, K., Abdel-Raheem, E., & Khalid, M.  (2008). Computationally efficient methods for blind decision feedback equalization of QAM signals. AEU-International Journal of Electronics and Communications, 62(5), 374-385.

18. Banović, K., Khalid, M. , & Abdel-Raheem, E. (2007). A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators. Digital Signal Processing, 17(6), 1071-1088.

19. Lee, R., Abdel-Raheem, E., & Khalid, M.  (2006). Computationally-Efficient DNLMS-Based Adaptive Algorithms for Echo Cancellation Application. JCM, 1(7), 1-8.

20. Banovic, K., Abdel-Raheem, E., & Khalid, M.  (2005). A novel radius-adjusted approach for blind adaptive equalization. IEEE Signal Processing Letters, 13(1), 37-40.

21. Khalid, M., & Rose, J. (2000). A novel and efficient routing architecture for multi-FPGA systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(1), 30-39.

Conferences

1. Smith Shawn; Khalid, M., Automated Generation and Integration of AUTOSAR RTE Configurations, 2022 IEEE Canadian Conference on Electrical and Computer Engineering, 2022.

2. Naimi, H; Akilan, T; Khalid, M., Fast Traffic Sign and Light Detection using Deep Learning for AutomotiveApplications, 1-5, 2021, doi:10.1109/WNYISPW53194.2021.966128, 2021 IEEE Western New York Image and Signal Processing Workshop (WNYISPW).

3. Patel, Prit; Ahmadi, Arash; Khalid, M., Implementing An Improved Image Enhancement Algorithm On FPGA, 2021 IEEE Canadian Conference on Electrical and Computer Engineering, 2021.

4. Siddhant Luthra, Mohammed A. S. Khalid, Mohammad Abdul Moin Oninda: FPGA-Based Evaluation and Implementation of an Automotive RADAR Signal Processing System using High-Level Synthesis, CCECE 2020: 1-6.

5. Sreeram, U., Khalid, M., and Noczensky, J., "Automated Generation of AUTOSAR ECU Configurations Using Xtend: Watchdog Driver Example," SAE Technical Paper 2020-01-1335, 2020 

6. Mohammad Abdul Momen, Mohammed A. S. Khalid, Mohammad Abdul Moin Oninda: FPGA-Based Acceleration of Expectation Maximization Algorithm Using High-Level Synthesis, DASIP 2019: 41-46 

7. Liu, L., & Khalid, M. (2018, August). Acceleration of K-Nearest Neighbor Algorithm on FPGA using Intel SDK for OpenCL. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 1070-1073). IEEE.

8. Alsaid, S., Abdel-Raheem, E., Khalid, M., & Mayyas, K. (2017, April). Variable tap-length algorithm using lattice structured lms adaptive filters. In 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE) (pp. 1-5). IEEE.

9. Zereen, S., Lal, S., Khalid, M., & Chowdhury, S. (2016, February). An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar. In Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 278-278). ACM.

10. Kashif, A., & Khalid, M.  (2016, October). Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures. In 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 1-4). IEEE.

11. Janik, I., & Khalid, M.  (2016, October). Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL. In 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 1-4). IEEE.

12. Janik, I., Tang, Q., & Khalid, M. (2015, May). An overview of altera sdk for opencl: A user perspective. In 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE) (pp. 559-564). IEEE.

13. Murawski, M., Priya, R. J., & Khalid, M. (2015, May). Design and evaluation of Avalon compatible adapter and parameterizable NoC router for FPGAs. In 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE) (pp. 553-558). IEEE.

14. Weiying Zeng, Mohammed A. S. Khalid, Sazzadur Chowdhury: A qualitative comparison of FlexRay and Ethernet in vehicle networks, CCECE 2015: 571-576 

15. Lee, R., Khalid, M. , & Abdel-Raheem, E. (2014, December). Configurable hardware implementation of a pipelined DNLMS adaptive filter. In 2014 26th International Conference on Microelectronics (ICM) (pp. 9-12). IEEE.

16. Singh, B. K., Tepe, K. E., & Khalid, M.  (2014, January). Control mechanism to solve false blocking problem at MAC layer in wireless sensor networks. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems (pp. 288-293). IEEE.

17. Imbewa, A., & Khalid, M.  (2013, August). FLNR: A fast light-weight NoC router for FPGAs. In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 445-448). IEEE.

18. Thangarajah, K., Shahrrava, B., & Khalid, M.  (2011, May). A novel simplified Log-MAP algorithm suitable for hardware implementation of turbo decoding. In 2011 24th Canadian Conference on Electrical and Computer Engineering (CCECE)(pp. 001463-001465). IEEE.

19. Mike Brugge and Mohammed A.S. Khalid. 2010. Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). In Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays (FPGA ’10). ACM, New York, NY, USA, 292-292. 

20. Le, T., & Khalid, M.  (2009, June). NoC prototyping on FPGAs: A case study using an image processing benchmark. In 2009 IEEE International Conference on Electro/Information Technology (pp. 441-445). IEEE.

21. Al Rayahi, O. A., & Khalid, M.  (2009, June). UWindsor Nios II: a soft-core processor for design space exploration. In 2009 IEEE International Conference on Electro/Information Technology (pp. 451-457). IEEE.

22. Zhang, L., Fresse, V., Khalid, M. , Houzet, D., Ahmadi, M., Legrand, A. C., & Fischer, V. (2009, July). Evaluation of noc dedicated to multispectral image data communication. In 2009 International Symposium on Signals, Circuits and Systems(pp. 1-4). IEEE.

23. Zhang, L., Fresse, V., Legrand, A. C., & Khalid, M. (2009, August). GALS NoC architectures on FPGA dedicated to multispectral image applications. In 2009 17th European Signal Processing Conference (pp. 978-982). IEEE.

24. Tong, J. G., & Khalid, M.  (2007, April). A comparison of profiling tools for FPGA-based embedded systems. In 2007 Canadian Conference on Electrical and Computer Engineering(pp. 1687-1690). IEEE.

25. Yazdanshenas, A., & Khalid, M.  (2007, August). A new scheduling algorithm for processor-based logic emulation systems. In 2007 50th Midwest Symposium on Circuits and Systems (pp. 1505-1508). IEEE.

26. Banovic, K., Khalid, M. , & Abdel-Raheem, E. (2007, December). FPGA implementation of a configurable complex blind adaptive equalizer. In 2007 IEEE International Symposium on Signal Processing and Information Technology(pp. 150-153). IEEE.

27. Tong, J. G., & Khalid, M.  (2007, December). Profiling CAD tools: A proposed classification. In 2007 Internatonal Conference on Microelectronics (pp. 253-256). IEEE.

28. Khalid, M. , & Salitrennik, V. (2006, December). Scalability Evaluation of a Hybrid Routing Architecture for Multi-FPGA Systems. In 2006 International Conference on Microelectronics (pp. 162-165). IEEE.

29. Tong, J. G., Anderson, I. D., & Khalid, M.  (2006, December). Soft-core processors for embedded systems. In 2006 International Conference on Microelectronics (pp. 170-173). IEEE.

30. Anderson, I. D., & Khalid, M.  (2006, May). Design Space Exploration using Parameterized Cores: A Case Study. In 2006 Canadian Conference on Electrical and Computer Engineering (pp. 1893-1896). IEEE.

31. Banovic, K., Lee, R., Abdel-Raheem, E., & Khalid, M. (2005, August). Computationally-efficient methods for blind adaptive equalization. In 48th Midwest Symposium on Circuits and Systems, 2005. (pp. 341-344). IEEE.

32. Banovic, K., Khalid, M. , & Abdel-Raheem, E. (2005, August). FPGA-based rapid prototyping of digital signal processing systems. In 48th Midwest Symposium on Circuits and Systems, 2005. (pp. 647-650). IEEE.

33. Xu, Y., & Khalid, M.  (2005, August). QPF: efficient quadratic placement for FPGAs. In International Conference on Field Programmable Logic and Applications, 2005. (pp. 555-558). IEEE.

34. Banovic, K., Abdel-Raheem, E., & Khalid, M.  (2005, June). Hybrid methods for blind adaptive equalization: new results and comparisons. In 10th IEEE Symposium on Computers and Communications (ISCC’05) (pp. 275-280). IEEE.

35. Khalid, M. , & Rose, J. (1999, April). Hardwired-clusters partial-crossbar: A hierarchical routing architecture for multi-FPGA systems. In International Parallel Processing Symposium (pp. 597-605). Springer, Berlin, Heidelberg.

36. Khalid, M. , & Rose, J. (1998, March). A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems. In Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays(pp. 45-54). ACM.

37. Khalid, M. , & Rose, J. (1997, December). Experimental evaluation of mesh and partial crossbar routing architectures for multi-FPGA systems. In Proceedings of the Sixth IFIP International Workshop on Logic and Architecture Synthesis (IWLAS’97) (pp. 119-127).

38. Khalid, M. , & Rose, J. (1995). The effect of fixed I/O pin positioning on the routability and speed of FPGAs. University of Toronto. Computer Systems Research Institute.