Software Based

This project is fully software based. I recorded different sound of mine and then analyzed those sound using MATLAB software. I used basic operations of speech signal processing in this project to determine the fundamental frequency and pitch of a signal. Autocorrelation and Cepstrum are time domain analysis. I determined fundamental frequency from these two analyses. Fast Fourier Transform and Periodogram are frequency domain analysis. I detected pitch of the signal by the analysis of PSD.

This project includes the design of a 9-bit parity generator/checker. To complete this project, I used Cadence Virtuoso software which includes schematic, layout, DRC check, LVS check, av extracted view, I/O cell, and Verilog code.

Here, Parity is used to identify errors in case of transmission of data that is caused by noise or other disturbances. A parity bit is an extra bit that is added to a data word and can be either odd or even parity. In an even parity system, the sum of all the bits (including the parity bit) is an even number. In an odd parity system, the sum of all the bits must be an odd number. The circuit that creates the parity bit at the transmitter is called the parity generator. The circuit that determines if the received data is correct is the parity checker.

Parity is good for detecting a single-bit error only. The parity generator and the parity checker can both be built using Exclusive-OR gates. To generate even parity the bits of data are Exclusive-ORed together in groups of two until there is only a single output left. This output is the parity bit. To generate odd parity, simply invert the even parity. The last gate can be an Exclusive-NOR gate. To check parity first a new parity bit must be generated over the date that was received. This parity bit is then compared to the received parity bit. If they are the same, then all is okay. The comparison can be done with an Exclusive-OR gate.

In my Level-3 Term-1, I designed a 100 kVA, 3 phase, 50 Hz, 11 KV/415 V, delta/star distribution transformer where I calculated no load current, efficiency at 750C on full load,75% load and 50% load at unity power factor; Votage regulation on full load at 750C at unity power factor and at 0.8 power factor lagging by using MATLAB.