Embedded Files
Week 1 {1/21 & 1/23}
1/21
- Syllabus week
- Created google site for DSD
- Linked GitHub to google site
- Discussed Ch. 1 of the book
1/23
- Downloaded & installed Vivado
- Discussed Ch. 2 of the book
Week 2 {1/28 & 1/30}
1/28
- Discussed Ch. 3 of the book
1/30
- Discussed Ch. 4 of the book
Nerdy Dave
Nerdy Dave
This is a complete guide on installing, running, and simulating a VHDL circuit on Windows using the two free and open source EDA tools - GHDL & GTKWave.
Week 3 {2/4 & 2/6}
2/4
- Nexys A7 setup was discussed
- Lab 1 as well as Project 1 were explained in further detail (Seven Second Decoder)
- Discussed Ch. 5 of the book
2/6
- Copied leddec.vhd & leddec.xdc from Professor Lu's GitHub
- Code was synthesized, implemented & bitstream was generated on Vivado
Week 4 {2/11 & 2/13}
2/11
- Nexys A7 was borrowed in order to complete the Part 1 of Lab 1
- Set up and powered Nexys A7 board
- Set up configuration file leddec.bit and loaded it into the FPGA
- Used sliders 0 to 3 in order to determine 4-bit hex digit
2/13
- Part 2 of Lab 1 was completed
- As of right now, labs are meant to get the user familiar with the Nexys A7 Board as well as Vivado
- Code is being copied and pasted for lab 1
Week 5 {2/20}
2/20
- Started to work on Lab 2: Four - Digit Hex Counter
- Build a four-digit (16-bit) counter to display its value on 7-segment displays
Week 6 {2/25 & 2/27}
- Researched Lab 3 and how I could reprogram ball.vhd source in order to finish assignment
Week 7 {No classes held: Professor Lu traveled to India}
Week 8 {Spring Break}
Week 9 {3/17 & 3/19}
3/17
- Started to work on Lab 3: Bouncing Ball
- Spoke on how to run Vivado without FPGA board
3/19
- Started work on Lab 4: Hex Calculator
- Researching project ideas in order to wrap up a proposal
Week 11 {3/24 & 3/26}
3/24
- Need to upload lab work and source code / documentation to GitHub account
3/26
- Started to work on Lab 5: Digital-to-Analog Converter (DAC) Siren
- Need to upload work from Labs 3 and 4 onto website and GitHub
Week 12 {3/31 & 4/2}
3/31
- Began researching how to execute Lab 6: Video Game "PONG"
- difficulty in attaining a potentiometer and extra material that are compatible with the FPGA board.
- Goal is to complete all labs and begin to focus on final project
4/2
- Difficulty uploading code onto the programmable board due to unnoticed hardware changes on PC
- Drivers that use the USB port to program the FPGA were non-functioning and spent a couple of hours researching solution
- Needed to uninstall and reinstall Xilinx Programmable Drivers back onto PC that were last installed when the Xilinx package was.
Week 13 {4/7 & 4/9}
4/7
- Found an old VGA cord and compatible monitor in order to test Lab 3
4/9
- Decided to separate weekly progress and labs so I will be reorganizing website
- Uploaded lab progress from Labs 1-3 onto my GitHub
- Deleted old repository and created a new one and updated the GitHub link on the main page.
- Goal is to finish all labs by the weekend
Week 14 {4/14 & 4/17}
4/14
- Completed Lab 3 and was able to finally insert a signal in order to change the direction of the ball toward the x-direction.
- Working on project alongside following labs
- Having trouble to connect the keyboard within my space invaders game. Need further research.
4/17
- Still having issues with the keyboard integration on the FPGA
- I wanna say it's because I'm using a wireless keyboard to be playing this instead wired but I have no idea whether that's the case.
Week 15 {4/21 & 4/23}
4/21
- Completed Lab 4 but was unable to test since I am missing the keypad equipment.
- Completed Lab 5
- Teamed up with Ryan McAliney for the final project since we had similar idea. Said he would take a look at keyboard.
- Did more research into solving the keyboard issue and will attach my finding to Useful Links along with the description of the links and any videos I can find in order to document the issue and maybe find a solution along the way.
- Uploaded Labs 3 & 4 on my GitHub
4/23
- It says that firmware in the board should support the USB/Keyboard function so other than specifying the USB HID constraint in the .xdc file and having a .vhd file to give the keys certain functions within the Top_Module. Still getting errors though.
Week 16 {4/28 & 4/30}
4/28
- Completed Lab 6, and uploaded documentation Lab 5 and 6 on website Lab page as well as GitHub.
- Final week is focused on getting keyboard to work for Space Invaders final project.
- Interesting news article posted in References indicates that academic researchers said they found a security flaw in FPGA chipsets sold by US company Xilinx, which is today's FPGA market leader and the same boards we use for DSD.
- Researchers say Starbleed attacks require physical access to the FPGA's JTAG port but if the FPGA bitstream is loaded from a microcontroller or another network source, attacks can be carried out remotely by targeting the location from where the bitstream is loaded, which in many cases may be available over a network or the internet, unlike the FPGAs themselves.
By Chris Williams, Editor in Chief 1 Oct 2019 at 16:00
4/30
If you hate writing Verilog, VHDL, and other hardware design languages, used to craft computer chips and configure FPGAs, you're far from the only one.
This Register vulture wrote Verilog for gate arrays in the early 2000s, and how did that work out? He ran screaming into the, at the time, more exhilarating world of journalism. Your humble hack wasn't the only one loathing these design languages: enough application-level software developers have now made their unhappiness with Verilog et al clear to FPGA design house Xilinx that the biz has had a rethink of its tooling.
As such, Xilinx has said it has rejigged its software to allow application programmers to more easily configure its FPGAs using a high-level language, particularly if they want to use Xilinx chips to accelerate machine-learning algorithms.
The goal is to allow engineers way up the stack to customize FPGAs to accelerate their algorithms, be them machine-learning inference or heuristic packet filters, or whatever, in hardware, without having to know how to write painful hardware design code. Application code can then offload parts of their processing to these chips, which perform the algorithms fast in hardware.
As well as Vitis, Xilinx is also launching developer.xilinx.com some time soon with more resources, and has a load of Vitis libraries and other stuff on GitHub, too.
Week 17 {5/5}
5/5
- Final review of work completed throughout the semester.
- Completed changes on project page suggested by Professor Lu.
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