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If you hate writing Verilog, VHDL, and other hardware design languages, used to craft computer chips and configure FPGAs, you're far from the only one.

This Register vulture wrote Verilog for gate arrays in the early 2000s, and how did that work out? He ran screaming into the, at the time, more exhilarating world of journalism. Your humble hack wasn't the only one loathing these design languages: enough application-level software developers have now made their unhappiness with Verilog et al clear to FPGA design house Xilinx that the biz has had a rethink of its tooling.

As such, Xilinx has said it has rejigged its software to allow application programmers to more easily configure its FPGAs using a high-level language, particularly if they want to use Xilinx chips to accelerate machine-learning algorithms.

The goal is to allow engineers way up the stack to customize FPGAs to accelerate their algorithms, be them machine-learning inference or heuristic packet filters, or whatever, in hardware, without having to know how to write painful hardware design code. Application code can then offload parts of their processing to these chips, which perform the algorithms fast in hardware.

As well as Vitis, Xilinx is also launching developer.xilinx.com some time soon with more resources, and has a load of Vitis libraries and other stuff on GitHub, too.

Xilinx FPGAs like the 7-series (families Spartan, Artix, Kintex and Virtex) and 6-series (Virtex) were found to be vulnerable.

Researchers say the Starbleed vulnerability allows an attacker to crack the bitstream encryption and tamper with the operations stored inside the bitstream, allowing the attacker to load their own malicious code on vulnerable devices.

"On these devices, the bitstream encryption provides authenticity by using an SHA-256 based HMAC and also provides confidentiality by using CBC-AES-256 for encryption," researchers said.

"By our attack, we can circumvent the bitstream encryption and decrypt an assumedly secure bitstream on all Xilinx 7-Series devices completely and on the Virtex-6 devices partially."

Researchers say Starbleed attacks require physical access to the FPGA's JTAG port; however, if the FPGA bitstream is loaded from a microcontroller or another network source, attacks can be carried out remotely by targeting the location from where the bitstream is loaded, which in many cases may be available over a network or the internet, unlike the FPGAs themselves.