Hardware Implementation of Pseudo Random Number Generator Based on Chaotic Iteration

• January 2018

• Thesis for: Phd Computer Science

• Advisor: Jean-François Couchot

In this thesis, we designed pseudo-random number generators (PRNGs) based on chaotic iterations to be deployed on hardware support such as FPGA or ASIC. These generators can be seen as post-processing of existing generators and thus transform a sequence of numbers, the input, into another, the output. The dependency between these two sequences has been proven chaotic according to Devaney: the effects of one bit change in the input cannot be predicted in the long term on output. Through the hardware implementations, we have been able to provide compact, very high speed, secure and reconfigurable PRNGs. A state of the art of the hardware implementations of PRNG’s was first carried out. All of them have been compared, after being fully implemented in FPGA, in a complete platform that we created. This last one allowed to compare the different hardware PRNGs, and in particular to carry out statistical tests on the outputs. New generators based on chaotic iterations (CI) were then designed and integrated into this platform. The embedded iterated function is built by removing an Hamiltonian cycle from an N-cube, the whole being followed by a permutation. Resulting generators generally have a better statistical profile than embedded ones, while running at a similar speed. Among the PRNGs able to pass the most difficult battery of statistical tests (TESTU01), those ones are the fastest in the world and the only ones to be chaotic. We have finally implemented them on numerous hardware supports: 65-nm ASIC circuit and FPGA Zynq.