CDTA

Up to 2020

Centre de Développement des Technologie Avancées, Alger (Algeria) 

Member of the research project “Platform of IP-VLSI for Algerian universities”, Team Methods Binary Arithmetic for Numeric Applications, Division System Architecture and Multimedia.

· Development of new algorithms based on chaotic iterations and elliptic curves for lightweight cryptography applications.

01/01/2014–31/12/2016

Centre de Développement des Technologie Avancées, Alger (Algeria) 

Member of the research project “IP Creation for Linear Systems”, Team Methods Binary Arithmetic for Numeric Applications, Division System Architecture and Multimedia.

·         Team leader in Design and implementation Hardware of Pseudo Number Random Generator PNRG based on Chaotic Iteration

01/01/2014–01/12/2016

Member of the research project “VLSI IPs for Bit Width Optimization”, Team Methods and tools for the design of circuits and integrated systems, Division Microelectronics and Nanotechnologies.

·      Team leader in Design and verification to physical implementation RTLGDS2 of the Bit-With Optimization IP core.

01/01/2014–31/12/2016

Member of the research project “Implementation of techniques and approaches for integration into SoCs”, Team Methods and tools for the design of circuits and integrated systems, Division Microelectronics and Nanotechnologies.

·       Team leader in Physical implementation RTL-GDS2 and Sign-off of a Low Power SoC based OpenRISC processor for VoIP applications.

04/01/2010–31/12/2013

Member of the research project " Conception and implementation of a system -on-chip for a VOIP application based on open source concepts and OpenCores", Team Reconfigurable Circuit and System on Chip (SOC), Division Microelectronics and Nanotechnologies.

·    Team leader in implementation and test of SoC based on “OpenRISC-1200-V3 processor, UART, ETHMAC, DEGUG, SPI, ROM, DDR2, PS2, AC97, GPIO, I2C, Wishbone” in FPGA,

· Team leader for embedded Linux Kernel-3.x in SoC on FPGA Virtex5,

· Team member in embedded and porting the VoIP-Asterisk application and Responsible in embedded other application as “Speech Recognition” on FPGA,

· Team leader in Conception Schematics and placements of two PCB based on Virtex5 XC5VLX50-1FFG676 FPGA (1RG45 12-layer & 4RG45 16-layer) using Altium Designer.

· Team member in Implementing ASIC of the SoC based on OpenRISC processor using Cadence-Synopsys Flow and TSMC 180n & UMC LL 65nm technologies.

01/10/2011–01/11/2012

Member of the cooperation research project "Design and implementation of a smart card on a FPGA", Division Microelectronics and Nanotechnologies, Centre of Development for Advanced Technology (CDTA) and HB Technologie, Alger, Algeria.

· Team leader of collaboration between CDTA and HB Company in HW conception and implementation of a Smart Card in FPGA (s3esk) using 8051 and ISO7816-3 protocol in VHDL (HB responsible in SW part),

· Team leader in implementation and optimization a free 8051 microcontroller from Opencores and following HB-Technologies specification,

· Team leader in an implementation from crash of the ISO protocol 7816-3 and following HB-Technologies specification.