I served as Program Chair for ISMM 2020 and as co-organizer of the ML for Systems Workshop at NeurIPS 2020. I am also serving on the PC for NeurIPS 2021, HPCA 2021 (industry track), MLSys 2022 and EuroSys 2022. I have previously served on the PC for PLDI 2019, ICPP 2020, NeurIPS 2020, ISCA 2021 and ICML 2021, the ERC for ISCA 2020, the ERC for ASPLOS 2019, 2020 and 2021, the ERC for PLDI 2018, the AEC for CGO 2015 and PPoPP 2015, and the PC for TinyToCS Vol. IV.
I have been involved with the RISC-V project since joining the Berkeley Architecture Group in 2011. I stay involved in the RISC-V community, serve as a member of the Technical Committee and am serving as the chair of the J Extension Working Group, which investigates extensions for JITed and interpreted languages in RISC-V. I am also a member of the Software Working Group and maintain the RISC-V Yocto port.