I have served on the organizing committees of several conferences and workshops:
Industry Track Co-Chair for MLSys'26.
General Chair for ISMM'25.
WACI Chair for ASPLOS'25.
Vice Program Chair for ASPLOS'25.
Co-organizer of the Young Architect Workshop (YArch) at ASPLOS'24.
Co-founder and co-organizer of the Practical Adoption Challenges of ML for Systems in Industry (PACMI) Workshop at MLSys'22 and MLSys'23.
Co-organizer of the ML for Systems Workshop at NeurIPS (2020-2022), Steering Committee (2023-).
Program Chair for ISMM'20.
I have also served on various PCs and ERCs:
PC: PLDI 2026, ASPLOS 2026, OSDI 2025, HotOS 2025, MLSys 2025, SOSP 2024, ASPLOS 2024, MLSys 2024, EuroSys 2024, OSDI 2023, Micro Top Picks 2023, MLSys 2023, ISCA 2022, MLSys 2022, EuroSys 2022, ISCA 2021, ICML 2021, NeurIPS 2021, HPCA 2021 (industry track), ICPP 2020, NeurIPS 2020, PLDI 2019
ERC: ISCA 2020, ASPLOS 2019, 2020 and 2021, PLDI 2018
Others: AEC for CGO 2015 and PPoPP 2015, PC for TinyToCS Vol. IV.
I have been involved with the RISC-V project since joining the Berkeley Architecture Group in 2011. I stay involved in the RISC-V community and serve as Google's Board of Directors Alternate for RISC-V International. I am also the chair of the JITed and Dynamic Languages SIG (formerly known as J Extension Working Group), which investigates extensions for JITed and interpreted languages in RISC-V.