With silicon transistors nearing their scaling limits, researchers are turning to 2D materials — atomically thin semiconductors that preserve outstanding electronic performance — to keep Moore’s Law alive.

A recent breakthrough from Penn State University marks a significant milestone: the successful demonstration of a computer built entirely from 2D materials, substances just one atom thick. The research team designed a functioning CMOS logic circuit using 2D semiconductors like molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂) — materials known for retaining exceptional electrical properties at atomic thickness. Unlike traditional silicon-based transistors, which suffer from performance degradation at extreme scaling, 2D materials offer superior electrostatics and minimal short-channel effects, even at nanometer dimensions. The resulting 2D computer operates at low voltages, consumes very little power, and performs logic operations at up to 25 kHz — all without relying on bulk silicon.

While 2D electronics is still a young field, this achievement signals a promising path forward. With further optimization, such systems could enable ultra-efficient computing platforms for edge AI, IoT, and energy-constrained applications.

Could this mark the beginning of a post-silicon era in computing? Early results suggest the answer may be yes.

As Moore’s Law approaches its fundamental limits, the semiconductor industry faces a critical challenge—how can we continue scaling transistors below 3 nm while maintaining performance and efficiency? Conventional architectures, such as FinFETs and Nanosheet (NSH) FETs, encounter challenges related to increasing power consumption, parasitic capacitance, and gate control dynamics. In this context, Forksheet (FSH) FETs emerge as a promising advancement, poised to enhance transistor scaling for the upcoming generation of high-speed electronics. Furthermore, incorporating Negative Capacitance in these devices presents an opportunity to promote energy-efficient computing technologies.

A recent simulation-based study from the Emerging Nanoscale Device (END) research group at the University of Dhaka (Bangladesh) investigates the Negative Capacitance (NC) effect in sub-3-nm Forksheet FETs. The study emphasizes how the integration of a ferroelectric (FE) layer within the Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) structure significantly enhances device performance. This incorporation of the ferroelectric layer leads to noteworthy reductions in subthreshold swing (SS) and threshold voltage (Vth), while also improving the on-off current ratio (ION/IOFF) and increasing switching speed. Consequently, NC-FSH FETs present a compelling alternative to traditional transistor architectures. By combining 1D Landau-Khalatnikov (L-K) equations with 3D TCAD simulations, the study demonstrates that NC-FSH FETs surpass both standard Forksheet and NC-Nanosheet FETs, achieving:
✅ ∼62% reduction in SS  

✅ ∼63% lower Vth  

✅ ∼19.2% faster switching

By tackling fundamental scaling challenges, NC-FSH FETs are shaping the future of ultra-scaled digital logic applications, ensuring an optimal balance of power efficiency, performance, and scalability beyond the 3-nm node. Could this be the key to keeping Moore’s Law alive? The answer should be yes!

In 1995, the semiconductor industry faced a significant challenge—would Moore’s Law endure as transistors shrank below 100 nm? At that time, Chenming Hu, a professor at UC Berkeley, introduced FinFETs, a groundbreaking transistor design that stacked channels vertically, enhancing efficiency and gate control. This innovation extended the lifespan of traditional silicon scaling.

However, as transistor nodes shrink beyond 5 nm, FinFET technology encounters fundamental limits. Short-channel effects (SCEs) impair performance, and reducing silicon thickness introduces quantum confinement and mobility degradation. To address these challenges, researchers are now exploring Gate-All-Around (GAA) nanosheet FETs, which provide superior electrostatic control. 

A recent collaborative simulation study (NanoTCAD ViDES) from Università di Pisa (Italy) and Technische Universität Wien (Austria) investigates the potential of vertically stacked 2D nanosheet FETs (NS-FETs). These transistors utilize 2D materials like MoS₂, which are atomically thin yet highly conductive. Unlike silicon nanosheets, 2D materials resist mobility degradation and minimize leakage currents, facilitating extreme miniaturization without performance loss. Additionally, stacking 2D channels vertically increases transistor density while maintaining a small footprint—crucial for future AI and high-performance computing (HPC) applications. 

The findings confirm that GAA-FETs based on 2D materials provide a scalable, high-performance alternative to FinFETs. While challenges such as fabrication complexity and contact resistance remain, this advancement paves the way for the next era of nanoelectronics. Could 2D nanosheets be the key to extending Moore’s Law further? The research suggests that the answer may be yes.

As nanoelectronics advance, high-density, low-power interconnects become crucial. However, traditional copper interconnects face a major hurdle: as they become thinner, their resistivity increases, leading to energy loss and inefficiency.

A recent study from Stanford University challenges this limitation. Researchers found that ultrathin, non-crystalline niobium phosphide (NbP) films exhibit an unexpected decrease in electrical resistivity as their thickness is reduced—the opposite behavior of conventional metals. This effect is driven by surface conduction mechanisms that enable higher carrier density and mobility, making NbP a superior alternative to copper in nanoscale electronics.

Beyond its low resistivity, NbP can be deposited at relatively low temperatures (~400°C), ensuring compatibility with existing semiconductor manufacturing. While producing perfectly crystalline nano-wires remains challenging, even amorphous or slightly disordered NbP films retain the desired electrical properties.

This breakthrough opens new possibilities for high-performance, low-energy interconnects in next-generation microchips and AI hardware. Could NbP reshape the future of semiconductor interconnects? Recent studies hint that it just might!