Mathworks

The well known synchronous reference frame phase-locked loop (SRF-PLL) gives unsatisfactory performance during unbalanced and distrorted grid conditions. To improve the PLL performance, various approaches for extracting fundamental frequency components are addressed in literature. Few such approaches are

• Second Order Generalized Integrator (SOGI) based PLL

• Cascaded Delayed Signal Cancellation (CDSC) based PLL

• Multiple Delayed Signal Cancellation (MDSC) based PLL

The MATLAB-Simulink files of above three PLLs are provided in my Mathworks community profile.