Projects

Current Projects




Multi-FPGA System for Controlling and Error Correcting 100s of qubits

In the quest for practical quantum computing, addressing qubit errors is a significant challenge. Surface codes offer a solution by encoding qubits redundantly across physical qubits. Real-time error correction for large surface codes is challenging, but we employ FPGAs for parallel processing.


Our approach involves a distributed UF algorithm-based decoder and FPGA implementation for real-time error correction. We've developed Helios, a multi-FPGA architecture, to overcome single FPGA limitations. The prototype comprises seven ZCU106 FPGAs, enabling real-time QEC for large surface codes.


QEC demands tight latency constraints, with each decoding round completing in under 1000ns for superconducting qubits. Our recent modifications allow Helios to balance hardware resource usage and latency, achieving decoding faster than the rate of measurement for surface codes exceeding distances of 50.

Previous Projects




Fault Recovery in Theseus OS

In this project we implement and evaluate fault recovery in the Theseus Operating System (OS), a new OS developed from scratch. Theseus is a modern OS written from scratch in Rust that explores intralingual design, novel OS structure, and state management. Fault recovery is essential in Theseus as a faulty task can potentially corrupt any OS structure, in the absence of hardware provided isolation.

We implement a series of fault recovery mechanisms on Theseus that take increasingly drastic measures to recover, if recovery was unsuccessful at the previous stage. At first we fully unwind and restart faulty tasks. If the fault is persistent, we replace potentially corrupted modules by loading fresh copies of those modules from the disk to a different location in memory.

We evaluate Theseus’s ability to recover from faults by stress testing our fault recovery implementation in the presence of hardware faults. Furthermore, we show that Theseus can recover from faults occurring in core OS components, e.g., those that necessarily exist within a microkernel, which goes beyond the capabilities of existing works.





Minion : Retrofitting Mobile Sensing Systems with Analog Datapath

In continuous sensing systems, the analog readout circuit, especially the analog to digital convertor (ADC) dominates the power consumption. Yet most of the energy used by ADC is wasted as these systems are always on and discard most data after simple processing.

In this work we try to achieve minimal runtime energy overhead while preserving general-purpose expressiveness when using analog circuits for sensor data processing. Our key idea is a mixed-signal, programmable analog processor, between the sensors and the digital processor, which is responsible for early process and discard of data before the ADC. 

 I worked on designing the digital control path of the project and emulating it using FPGA



FPGA based architectures for Screen Content Coding

Screen content coding (SCC) extension to High Efficiency Video Coding (HEVC) offers substantial compression efficiency over the existing video coding standards for computer generated content. This gain is possible due to exploiting features such as repeated patterns, limited colors, highly saturated areas which are common in computer generated content. However, this gain in compression efficiency is achieved at the expense of further computational complexity with several resource hungry coding tools. Hence, extension of SCC to hardware encoders can be challenging.  

In this work we designed resource efficient hardware architectures for two key SCC tools, Intra Block Copy and Palette Coding. These architectures were emulated on a Virtex-7 FPGA 




FPGA based HEVC encoder

Higher compression efficiency in HEVC encoders comes with increased computational complexity, making real time encoding of high resolution videos a challenging task. This challenge can be addressed by software, yet hardware solutions are more appealing due to their superior performance and low power consumption. 

In this work we designed an FPGA based implementation of an all intra HEVC encoder, which can encode 8 bits per sample, 1920x1080 resolution, 30 frames per second raw video, that is viable in real time even at low operating frequencies. A major obstacle to real time encoding in available architectures is the dependency created by reference generation. 

In this work we designed a new three stage architecture to reduce these dependencies and increase parallelism. All modules can operate up to 200 MHz and the encoder can achieve real time encoding with a minimum operating frequency of 140 MHz in a Xilinx Zynq ZC706 FPGA.

A talk I gave on this work is available here