Namitha Liyanage
PhD candidate - Computer Science - Yale University
Quantum Error Correction and multi-FPGA architectures
ආයුබෝවන්...
AYUBOWAN... (Wish you a long life)
I am a PhD candidate at Computer Science Department in Yale University. I'm working with Professor Lin Zhong in Yale Efficient Computing Lab. My current research focuses on building scalable multi-FPGA systems for Quantum Error Correction and control.
Prior to joining Yale, I started my graduate studies at Rice University, Texas where I got my MSc in Electrical and Computer Engineering in 2020. I moved to Yale in the fall of 2020 to continue my work with my advisor.
In the summer of 2019, I interned at Google, Sunnyvale. Before starting graduate school I worked 2 years at Paraqum Technologies working as a hardware engineer working on developing FPGA based video encoders for HEVC standard.
Contact : namitha.liyanage@yale.edu
Office : 309 Arthur K. Watson Hall
Profiles : LinkedIn | Google Scholar| Github
Recent Updates
Gave an invited talk at the Kobe Quantum Error Correction Symposium in January 2024
Presented our paper titled "Scalable Quantum Error Correction for Surface Codes using FPGA" at QCE 2023 (PDF)
Francesco Battistel presented our work in the Error Correction workshop at QCE 2023.
Spend the summer at Qblox, Netherlands working on implementing our distributed Error decoder inside Qblox stack.
Present a poster on FPGA-based Quantum Error decoders at FCCM 2023.
Our latest work on distributed UF decoder is now available in the arxiv (PDF)
Research
Multi-FPGA System for Controlling and Error Correcting 100s of qubits
Updates: Our latest work is now available online
Scalable Quantum Error Correction for Surface Codes using FPGA
In the quest for practical quantum computing, addressing qubit errors is a significant challenge. Surface codes offer a solution by encoding qubits redundantly across physical qubits. Real-time error correction for large surface codes is challenging, but we employ FPGAs for parallel processing.
Our approach involves a distributed UF algorithm-based decoder and FPGA implementation for real-time error correction. We've developed Helios, a multi-FPGA architecture, to overcome single FPGA limitations. The prototype comprises seven ZCU106 FPGAs, enabling real-time QEC for large surface codes.
QEC demands tight latency constraints, with each decoding round completing in under 1000ns for superconducting qubits. Our recent modifications allow Helios to balance hardware resource usage and latency, achieving decoding faster than the rate of measurement for surface codes exceeding distances of 50.
For my past projects : Click Here
Education
2020 - : Yale University
PhD candidate in Computer Science
Master of Science in Computer Science (2022)
Master of Philosophy in Computer Science (expected 2023 December)
2017 - 2020 : Rice University
Master of Science in Electrical and Computer Engineering
2010 - 2015 : University of Moratuwa
Bachelor of the Science in Electronic and Telecommunication Engineering
(Rank 2 out of 100 students)
Professional Experience
FPGA engineering Intern (2023) at Qblox
Implemented a distributed union find decoder inside Qblox stack
Software Engineering Intern (2019) at Google
Worked on FPGA-based application acceleration
Associate Architect (2017 ), Electronic Engineer (2015 - 2017) at ParaQum Technologies (Pvt.) Ltd
Led a team of engineers that designed and developed a real-time all-intra HD HEVC encoder on FPGA
Worked on developing a 4K real-time FPGA-based HEVC decoder to support higher profiles
Worked on developing FPGA-based HEVC - Screen content coding encoder
Application Engineer (Consultancy basis) (2015 - 2017) at Wave Computing
Mapped machine learning algorithms to wave data-flow architecture (novel coarse-grained reconfigurable architecture) using in-house programming tools
Trainee Associate Electronic Engineer (2013-2014) at Zone 24x7 (Pvt.) Ltd
Designed handwriting pre-processing software to be integrated with a computer vision-based check processing library and a computer vision-based information extraction library. This work was judged as the best industrial training project in the Electronics and Telecommunication Category by the Institution of Engineers Sri Lanka for the year 2014
Publications
Namitha Liyanage, Yue Wu, Alexander Deters and Lin Zhong, "Scalable Quantum Error Correction for Surface Codes using FPGA", arXiv preprint arxiv:2301.08419, January 2023. Presented in IEEE Quantum Computing and Engineering (QCE), September 2023 (PDF)
Yue Wu, Namitha Liyanage and Lin Zhong, "An interpretation of Union-Find Decoder on Weighted Graphs", arXiv preprint arxiv:2211.03288, November 2022. (PDF)
Kevin Boos, Namitha Liyanage, Ramla Ijaz, and Lin Zhong, "Theseus: an experiment in operating system structure and state management," in Proc. USENIX Symposium on Operating Systems Design and Implementation (OSDI), November 2020. (Source code, PDF)
Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P.M.K. Tharaka, Geethan Karunaratne, R.M.A.U. Senarath, Ishantha Perera, Ashen Ekanayake and Ajith Pasqual, "High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension" in 'The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors' (ASAP), July 2017 (PDF)
Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera and Ajith Pasqual, "Real Time All Intra HEVC HD Encoder on FPGA" in 'The 27th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors' (ASAP), July 2016 (PDF)
Teaching
Teaching Fellow for Technology, Power, and Security: Political Challenges of the Computer Age (CPSC 310) : Yale University 2023
Teaching Fellow for Building Distributed Systems (CPSC 426/526) : Yale University : 2022
Teaching Fellow for Computer System Design (CPSC 429/529) : Yale University : 2021
Grader for Mobile and Embedded Systems (ECE 424/524) : Rice University 2018