NAMITHA LIYANAGE

PhD student - Computer Science - Yale University

ආයුබෝවන්...

AYUBOWAN... (Wish you a long life)


I am a PhD student at Computer Science Department in Yale University. I'm working with Professor Lin Zhong in Yale Efficient Computing Lab. My current research focuses on building scalable multi-FPGA systems for Quantum Error Correction and Qubit control & measurement.

I am originally from Colombo, Sri Lanka. I got my BSc from University of Moratuwa in Electronics and Telecommunication Engineering. I started my graduate studies at Rice University, Texas where I got my MSc in 2020. I moved to Yale in the fall of 2020 to continue my work with my advisor.

In the summer of 2019, I interned at Google, Sunnyvale. Prior to starting graduate school I worked 2 years at Paraqum Technologies working on developing FPGA based video encoders.


Contact : namitha.liyanage@yale.edu

Office : 309 Arthur K. Watson Hall

Profiles : LinkedIn | Google Scholar| Github

Current Research


Multi-FPGA System for Controlling 1000 qubits

A significant challenge in realizing a practical quantum computer is the errors in the quantum bits (qubits). A promising solution for quantum error correction is surface codes where a single qubit is redundantly encoded across multiple physical qubits. In addition to that a surface code patch contains stabilizers which keep track of errors in adjacent physical qubits. By decoding the stabilizer results the underlying error pattern can be identified.

A key challenge in the above process is the scalability of the decoder. Decoding process has strict latency bounds to keep up with rest of the system, which is in the range of 10s of microseconds. While large surface code patches can exponentially increase error correction capabilities, the size of a surface code patch will be limited by the decoding capability.

In our current research we are building a system with many FPGAs to overcome this scalability bottleneck. We chose FPGAs as they can perform parallel computations with very low deterministic latency, which is a necessity in real time decoding. We are also working on developing an algorithm that can be mapped across many FPGAs without getting bottlenecked by inter FPGA communication.

For my past projects : Click Here

Publications

  • Kevin Boos, Namitha Liyanage, Ramla Ijaz, and Lin Zhong, "Theseus: an experiment in operating system structure and state management," in Proc. USENIX Symposium on Operating Systems Design and Implementation (OSDI), November 2020. (Source code, PDF)


  • Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P.M.K. Tharaka, Geethan Karunaratne, R.M.A.U. Senarath, Ishantha Perera, Ashen Ekanayake and Ajith Pasqual, "High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension" in 'The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors' (ASAP), July 2017 (PDF)


  • Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera and Ajith Pasqual, "Real Time All Intra HEVC HD Encoder on FPGA" in 'The 27th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors' (ASAP), July 2016 (PDF)

Teaching

  • Teaching Fellow for Building Distributed Systems (CPSC 426/526) : Yale University : 2022


  • Teaching Fellow for Computer System Design (CPSC 429/529) : Yale University : 2021


  • Grader for Mobile and Embedded Systems (ECE 424/524) : Rice University 2018