Publications

61 SCI Journals (28 First Author)

24 International Conference Papers (3 Invited Papers)

11 Korea Conference Papers

5 US Patents (1 Granted) & 7 Korea Patents (5 Granted)

SCI Journals

• 1. K. Cho, H. Yun, K. Nam, C. Park, H. Jang, J.-S. Yoon, H.-C. Choi, M. S. Park, and R.-H. Baek, "Enhancement of ISPP efficiency using neural network-based optimization of 3-D NAND cell," IEEE Trans. Electron Devices, vol. 70, no. 7, pp. 3504-3510, Jul. 2023.

  2. C. Park, J.-S. Yoon, K. Nam, H. Jang, M. Park, and R.-H. Baek, "Investigation of program efficiency overshoot in 3D vertical channel NAND flash with randomly distributed traps," Nanomaterials, vol.13, no.9, pp. 1-13, Apr. 2023

  3. C. Park, J.-S. Yoon, K. Nam, H. Jang, M. S. Park, and R.-H. Baek, “Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data”, Mater. Sci. in Semiconductor Processing, vol. 157, no. 107333, Apr. 2023. 

  4. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, "Novel trench inner-spacer scheme to eliminate parasitic bottom transistors of silicon nanosheet FETs," IEEE Trans. Electron Devices, vol. 70, no. 2, pp. 396-401, Feb. 2023.

  5. K. Nam, C. Park, H. Yun, J.-S. Yoon, H. Jang, K. Cho, M. S. Park, H.-C. Choi, and R.-H. Baek, “Holistic optimization of trap distribution for performance/reliability in 3-D NAND flash using machine learning,” IEEE Access, vol. 11, pp. 7135-7144, Jan. 2023. 

  6. J. Lee, J.-S. Yoon, J. Lim, and R.-H. Baek, “Electrical coupling effect of forksheet FET for power, performance and area analysis,” IEEE Trans. Electron Devices, vol. 69, no. 12, pp. 7096-7101, Dec. 2022.

  7. S. Lee, J.-S. Yoon, and R.-H. Baek, “Nanowire diameter dependency of the variability in n/p silicon nanowire FETs with ultrashort gate-length of 15 nm,” IEEE Trans. Electron Devices, vol. 69, no. 12, pp. 6529-6534, Dec. 2022.

  8. S. Lee, J. Jeong, J.-S. Yoon, S. Lee, J. Lee, J. Lim, and R.-H. Baek, “Sensitivity of inner spacer thickness variations for sub-3-nm node silicon nanosheet field-effect transistors,” Nanomaterials, vol. 12, no. 3349, pp. 1-11, Sep. 2022.

  9. H. Jang, C. Park, K. Nam, H. Yun, K. Cho, J.-S. Yoon, H.-C. Choi, H.-J. Kang, M. S. Park, J. Sim, and R.-H. Baek, “Bi-directional LSTM neural network modeling of retention characterization in 3-dimensional triple-level cell NAND flash,” IEEE Trans. Electron Devices, vol. 69, no. 7, pp. 4241-4247, Aug. 2022.

  10. K. Nam, C. Park, J.-S. Yoon, K. Yang, M. S. Park, and R.-H. Baek, “Channel thickness and grain size engineering for improvement of variability and performance in 3D NAND flash memory,” IEEE Trans. Electron Devices, vol. 69, no. 7, pp. 3681-3687, Jul. 2022.

  11. H. Jang, H. Yun, C. Park, K. Cho, K. Nam, J.-S. Yoon, H.-C. Choi, and R.-H. Baek, “Extraction of device structural parameters through DC/AC performance using an MLP neural network algorithm,” IEEE Access, vol. 10, pp. 64408-64419, Jun. 2022. 

  12. K. Nam, C. Park, J.-S. Yoon, H. Yun, H. Jang, K. Cho, H.-J. Kang, M.-S. Park, J. Sim, H.-C. Choi, and R.-H. Baek, “Optimal energetic-trap distribution of nano-scaled charge trap nitride for wider Vth window in 3D NAND flash using a machine-learning method,” Nanomaterials, vol. 12, no. 1808, pp. 1-10, May 2022. 

  13. S. Lee, J.-S. Yoon, J. Lee, J. Jeong, H. Yun, J. Lim, S. Lee, and R.-H. Baek, “Novel modeling approach to analyze threshold voltage variability in short gate-length (15-22 nm) nanowire FETs with various channel diameters,” Nanomaterials, vol. 12, no. 1721, pp. 1-9, May 2022. 

  14. J.-S. Yoon, J. Jeong, S. Lee, J. Lee, S. Lee, J. Lim, and R.-H. Baek, “DC performance variations by grain boundary in source/drain epitaxy of sub-3-nm nanosheet field-effect transistors,” IEEE Access, vol. 10, pp. 22032-22037, Mar. 2022.

  15. J.-S. Yoon, J. Jeong, S. Lee, J. Lee, S. Lee, R.-H. Baek, and S. K. Lim, “Performance, power, and area of standard cells in sub 3 nm node using buried power rail,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 894-899, Mar. 2022. 

  16. J. Lee, J.-S. Yoon, J. Jeong, S. Lee, S. Lee, and R.-H. Baek, "Monolithic 3D 6T-SRAM based on newly designated gate and source/drain bottom contact schemes," IEEE Access, vol. 9, pp. 138192-138199, Oct. 2021.

  17. J. Kim, B. Ku, J.-S. Yoon, and S.-K. Lim, “An effective block pin assignment approach for block-level monolithic 3D ICs,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 1, pp. 26-34, Jun. 2021. 

  18. J. Lee, J.-S. Yoon, S. Lee, J. Jeong, and R.-H. Baek, “TCAD-based flexible fin pitch design for 3-nm node 6T-SRAM using practical source/drain patterning scheme,” IEEE Trans. Electron Devices, vol. 68, no. 3, pp. 1031-1036, Mar. 2021.

  19. J.-S. Yoon, S. Lee, H. Yun, and R.-H. Baek, “Digital/Analog performance optimization of vertical nanowire FETs using machine learning,” IEEE Access, vol. 9, pp. 29071-29077, Feb. 2021. 

  20. J. Jeong, J.-S. Yoon, and R.-H. Baek, “Analysis of TSV-induced mechanical stress and electrical noise coupling in sub 5-nm node nanosheet FETs for heterogeneous 3D-ICs,” IEEE Access, vol. 9, pp. 16728-16735, Jan. 2021.

  21. K. Nam, C. Park, J.-S. Yoon, H. Jang, M. S. Park, J. Sim, and R.-H. Baek, “Origin of incremental step pulse programming (ISPP) slope degradation in charge trap nitride based multi-layer 3D NAND flash,” Solid-State Electron., vol. 175, pp. 107930-1-6, Jan. 2021.

  22. J.-S. Yoon and R.-H. Baek, “A novel sub-5-nm node dual-workfunction folded cascode nanosheet FETs for low power mobile applications,” IEEE Access, vol. 8, pp. 196975-196978, Nov. 2020. 

  23. H. Yun, J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, "Neural network based design optimization of 14-nm node fully-depleted SOI FET for SoC and 3DIC applications," IEEE J. Electron Devices Soc., vol. 8, pp. 1272-1280, Nov. 2020.

  24. J.-S. Yoon and R.-H. Baek, “Device design guideline of 5-nm-node FinFETs and Nanosheet FETs for analog/RF applications,” IEEE Access, vol. 8, pp. 189395-189403, Oct. 2020. 

  25. H.-C. Choi, H. Yun, J.-S. Yoon, and R.-H. Baek, “Neural approach for modeling and optimizing of transistor in semiconductor manufacturing,” IEEE Access, vol. 8, pp. 159351-159370, Sep. 2020.

  26. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, “Threshold voltage variations induced by Si1-xGex and Si1-xCx of sub 5-nm node nanosheet field-effect transistors,” J. Nanosci. Nanotechnol., vol. 20, pp. 4684-4689, Aug. 2020.

  27. J.-S. Yoon, S. Lee, J. Lee, J. Jeong, H. Yun, and R.-H. Baek, "Reduction of process variations for sub-5-nm node fin and nanosheet FETs using novel process scheme," IEEE Trans. Electron Devices, vol. 67, no. 7, pp. 2732-2737, Jul. 2020.

  28. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, “Comprehensive analysis of source and drain recess depth variations on silicon nanosheet FETs for sub 5-nm node SoC application,” IEEE Access, vol. 8, pp. 35873-35881, Feb. 2020.

  29. S. Lee, J.-S. Yoon, J. Jeong, J. Lee, and R.-H. Baek, “Observation of mobility and velocity behaviors in ultra-scaled Lg=15 nm silicon nanowire field-effect transistors with different channel diameters,” Solid-State Electron., vol. 164, pp. 107740-1-6, Feb. 2020.

  30. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Sensitivity of source/drain critical dimension variations for sub 5 nm node fin and nanosheet FETs,” IEEE Trans. Electron Devices, vol. 67, no. 1, pp. 258-262, Jan. 2020.

  31. J.-S. Yoon, S. Lee, J. Lee, J. Jeong, H. Yun, B. Kang, and R.-H. Baek, “Source/Drain patterning FinFETs as solution for physical area scaling toward 5-nm node,” IEEE Access, vol. 7, pp. 172290-172295, Dec. 2019. 

  32. G. Kang, J.-S. Yoon (co-1st), G.-W. Kim, K. Choi, R.-H. Baek, T. Park, and J. Lim, “Electron trapping and extraction kinetics on carrier diffusion in metal halide perovskite thin films,” J. Mater. Chem. A, vol. 7, pp. 25838-25844, Sep. 2019.

  33. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Bottom oxide bulk FinFETs without punch-through-stopper for extending toward 5-nm node,” IEEE Access, vol. 7, pp. 75762-75767, Jun. 2019. 

  34. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Punch-through-stopper free nanosheet FETs with crescent inner-spacer and isolated source/drain,” IEEE Access, vol. 7, pp. 38593-38596, Apr. 2019. 

  35. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Metal source-/drain-induced performance boosting of sub-7-nm node nanosheet FETs,” IEEE Trans. Electron Devices, vol. 66, no. 4, pp. 1868-1873, Apr. 2019.

  36. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications,” Jpn. J. Appl. Phys., vol. 58, pp. SBBA12-1-5, Mar. 2019. 

  37. Y. Lee, H. Kwon, J.-S. Yoon, and J. Kim, “Overcoming ineffective resistance modulation in p-type NiO gas sensor by nanoscale Schottky contacts,” Nanotechnology, vol. 30, no. 11, pp. 115501-1-6, Jan. 2019. 

  38. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Systematic DC/AC performance benchmarking of sub-7-nm node FinFETs and nanosheet FETs,” IEEE J. Electron Devices Soc., vol. 6, pp. 942-947, Aug. 2018. 

  39. J.-S. Yoon and R.-H. Baek, “Study on random dopant fluctuation in core-shell tunneling field-effect transistors,” IEEE Trans. Electron Devices, vol. 65, no. 8, pp. 3131-3135, Aug. 2018. 

  40. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Multi-Vth strategies of 7-nm node nanosheet FETs with limited nanosheet spacing,” IEEE J. Electron Devices Soc., vol. 6, pp. 861-865, Jul. 2018. 

  41. J.-S. Yoon, “DC performance variations of SOI FinFETs with different Silicide thickness,” Adv. Cond. Matter Phys., vol. 2018, pp. 2426863-1-7, May 2018.

  42. H. Kwon, J.-S. Yoon (co-1st), Y. Lee, D. Y. Kim, C.-K. Baek, and J. K. Kim, “An array of metal oxides nanoscale hetero p-n junctions toward designable and highly-selective gas sensors,” Sensor and Actuator B, vol. 255, pp. 1663-1670, Feb. 2018. 

  43. J.-S. Yoon, K. Kim, M. Meyyappan, and C.-K. Baek, “Bandgap engineering and strain effects of core-shell tunneling field-effect transistors,” IEEE Trans. Electron Devices, vol. 65, no. 1, pp. 277-281, Jan. 2018. 

  44. S. Yoon, K. Kim, H. Cho, J.-S. Yoon, M. J. Lee, M. Meyyappan, and C.-K. Baek, “Polysilicon near-infrared photodetector with performance comparable to crystalline silicon devices,” Optics Express, vol. 25, no. 26, pp. 32910-32918, Dec. 2017. 

  45. J.-S. Yoon, K. Kim, M. Meyyappan, and C.-K. Baek, “Optical Characteristics of Silicon-based Asymmetric Vertical Nanowire Photo-detectors,” IEEE Trans. Electron Devices, vol. 64, no. 5, pp. 2261-2266, May 2017. 

  46. J. Choi, J.-S. Yoon, and C.-K. Baek, “Investigation of DC characteristics in polysilicon nanowire tunneling field-effect transistors,” J. Nanosci. Nanotechnol., vol. 17, pp. 3071-3076, May 2017. 

  47. H. Cho, K. Kim, J.-S. Yoon, T. Rim, M. Meyyappan, and C.-K. Baek, “Optimization of signal to noise ratio in silicon nanowire ISFET sensors,” IEEE Sens. J., vol. 17, no. 9, pp. 2792-2796, May 2017. 

  48. N. Hong, C. Park, D. Kim, K.-S. Jeong, J.-S. Yoon, B. Jin, M. Meyyappan, and J.-S. Lee, “Buffer effects of two functional groups against pH variation at aminosilanized electrolyte-oxide-semiconductor (EOS) capacitor,” Sensor and Actuator B, vol. 242, pp. 324-331, Apr. 2017. 

  49. J.-S. Yoon, K. Kim, T. Rim, and C.-K. Baek, “Performance and variations induced by single interface trap in 7-nm node nanowire FETs,” IEEE Trans. Electron Devices, vol. 64, no. 2, pp. 339-345, Feb. 2017. 

  50. T. Rim, K. Kim, H.-S. Cho, W. Jeong, J.-S. Yoon, Y. Kim, M. Meyyappan, and C.-K. Baek, “Electrical characteristics of doped silicon nanowire channel field-effect transistor biosensors,” IEEE Sens. J., vol. 17, no. 3, pp. 667-673, Feb. 2017. 

  51. J.-S. Yoon, K. Kim, and C.-K. Baek, “Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors,” Nat. Sci. Rep., vol. 7, pp. 41142-1-41142-7, Jan. 2017. 

  52. J.-S. Yoon, C.-K. Baek, and R.-H. Baek, “Process-induced variations of 10-nm node bulk nFinFETs considering middle-of-line parasitics,” IEEE Trans. Electron Devices, vol. 63, no. 9, pp. 3399-3405, Sep. 2016. 

  53. J.-S. Yoon, K. Kim, T. Rim, and C.-K. Baek, “Variability study of Si nanowire FETs with different junction gradients,” AIP Advances, vol. 6, pp. 015318-1-7, Jan. 2016. 

  54. J.-S. Yoon, E.-Y. Jeong, C.-K. Baek, Y.-R. Kim, J.-H. Hong, J.-S. Lee, R.-H. Baek, and Y.-H. Jeong, “Junction design strategy for Si bulk FinFETs for system-on-chip applications down to the 7-nm node,” IEEE Electron Device Lett., vol. 36, no. 10, pp. 994-996, Oct. 2015. 

  55. E.-Y. Jeong, J.-S. Yoon, C.-K. Baek, Y.-R. Kim, J.-H. Hong, J.-S. Lee, R.-H. Baek, and Y.-H. Jeong, “Investigation of RC parasitics considering middle-of-the-line in Si-bulk FinFETs for sub-14-nm node logic applications,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3441-3444, Oct. 2015. 

  56. J.-S. Yoon, T. Rim, J. Kim, K. Kim, C.-K. Baek, and Y.-H. Jeong, “Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors,” Appl. Phys. Lett., vol. 106, pp. 103507-1-5, Mar. 2015. 

  57. J.-H. Hong, S.-H. Lee, Y.-R. Kim, E.-Y. Jeong, J.-S. Yoon, J.-S. Lee, R.-H. Baek, and Y.-H. Jeong, “Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs,” Jpn. J. Appl. Phys., vol. 54, no. 4S, pp. 04DN05-1-5, Feb. 2015. 

  58. J.-S. Yoon, E.-Y. Jeong, S.-H. Lee, Y.-R. Kim, J.-H. Hong, J.-S. Lee, and Y.-H. Jeong, “Extraction of source/drain resistivity parameters optimized for double-gate FinFETs,” Jpn. J. Appl. Phys., vol. 54, pp. 04DC06-1-4, Jan. 2015. 

  59. J.-S. Yoon, T. Rim, J. Kim, M. Meyyappan, C.-K. Baek, and Y.-H. Jeong, “Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths,” Appl. Phys. Lett., vol. 105, pp. 102105-1-4, Sep. 2014. 

  60. S.-H. Lee, Y.-R. Kim, J.-H. Hong, E.-Y. Jeong, J.-S. Yoon, C.-K. Baek, D.-W. Kim, J.-S. Lee, and Y. H. Jeong, “Investigation of low-frequency noise in p-type nanowire FETs: effect of switched biasing condition and embedded SiGe layer,” IEEE Electron Device Lett., vol. 35, no. 7, pp. 702-704, Jul. 2014. 

  61. C.-H. Park, M.-D. Ko, K.-H. Kim, S.-H. Lee, J.-S. Yoon, J.-S. Lee, and Y. H. Jeong, “Investigation of low-frequency noise behavior after hot-carrier stress in an n-channel junctionless nanowire MOSFET,” IEEE Electron Device Lett., vol. 33, no. 11, pp. 1538-1540, Nov. 2012.  

International Conferences

• 1. S. M. Shaji, L. Zhu, J.-S. Yoon, and S. K. Lim, "A comperative study on front-side, buried and back-side power rail topologies in 3nm technology node," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Vienna, Austria, Sep. 2023.

  2. K. Nam, C. Park, J.-S. Yoon, H. Yun, H. Jang, K. Cho, H. Kang, M. S. Park, H. Oh, J. Sim, and R.-H. Baek, "Optimal energetic trap distribution of charge trap nitride for wider Vth window in 3D NAND Flash using machine learning methodology," International Conference on Solid-State Devices and Materials, Virtual, Japan, Sep. 2021.

  3. H. Yun, J.-S. Yoon, H.-C. Choi, and R.-H. Baek, "Neural network based 14-nm node fully-depeleted FET design for AC applications of SoC and 3DIC," NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2020.

  4. J. Jeong, J.-S. Yoon, S. Lee, J. Lee, and R.-H. Baek, "Through silicon via (TSV)-to-transistor noise coupling characterizations for sub 5-nm node fin and nanosheet FETs in 3D-IC," NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2020.

  5. J. Lee, J.-S. Yoon, S. Lee, J. Jeong, and R.-H. Baek, "SRAM performance variations induced by source/drain mole fraction change of sub 5-nm node silicon nanosheet field-effect transistors," NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2020.

  6. H. Yun, J.-S. Yoon, J. Jeong, S. Lee, H.-C. Choi, and R.-H. Baek, "Neural network based design optimization of 14-nm node fully-depleted SOI FET for SoC and 3DIC applications," Electron Devices Technology and Manufacturing, Penang, Malaysia, Mar. 2020. 

  7. J.-S. Yoon, S. Lee, J. Jeong, and R.-H. Baek, "Critical dimension variations of sub 5-nm node fin and nanosheet FETs," NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2019.

  8. S. Lee, J.-S. Yoon, J. Lee, J. Jeong, R.-H. Baek, "Comparison of virtual source velocity and apparent mobility in shrunk Lg=15 nm n/p-SNWFETs with various diameters," NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2019.

  9. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, “Impact of mechanical stress induced by through-silicon vias on performance variations of 5-nm node nanosheet FETs,” NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2019.

  10. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, “The effects of realistic u-shaped source/drain on dc/ac performances of silicon nanosheet FETs for sub 5-nm node SoC applications,” Electron Devices Technology and Manufacturing, Singapore, Mar. 2019. 

  11. (Late news) J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Nanosheet number and width optimization of multi stacked nanosheet FET for 7-nm node SoC application,” International Conference on Solid-State Devices and Materials, Tokyo, Japan, Sep. 2018.

  12. (Invited) J.-S. Yoon and C.-K. Baek, “Vertical nanowire tunneling field-effect transistors adopting core-shell structure with strain effects,” IEEE International Nanoelectronics Conference, Kuala Lumpur, Malaysia, Jan. 2018.

  13. H. Kwon, J.-S. Yoon, Y. Lee, D. Y. Kim, C.-K. Baek, and J.-K. Kim, “An array of metal oxides nanoscale hetero p-n junctions toward designable and highly-selective gas sensors,” MRS Fall Meeting, Boston, USA, Nov. 26 – Dec. 1, 2017.

  14. (Invited) J.-S. Yoon, K. Kim, and C.-K. Baek, “Silicon-based tunneling field-effect transistors for ultra-low power applications,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Gyeongju, Korea, Jul. 2017.

  15. J.-S. Yoon, K. Kim, and C.-K. Baek, “Silicon tunneling field-effect transistors having core-shell structure,” NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2017.

  16. S. Yoon, K. Kim, H. Cho, J.-S. Yoon, M. Meyyappan, and C.-K. Baek, “Investigation of nano-scale grain boundary effect on polysilicon near-infrared photodetector,” NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2017.

  17. S. Lee, K. Kim, M. Seo, J.-S. Yoon, M. Meyyappan, and C.-K. Baek, “Thermal conductivity analysis of vertical Si nanowire array using differential 3w method,” NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2017.

  18. W. Jeong, J.-S. Yoon, K. Kim, and C.-K. Baek, “Gas sensitivity analysis of single ZnO nanowire gas sensor having different defect density, dimension and material properties,” NANO KOREA, KINTEX, Ilsan, Korea, Jul. 2017.

  19. N. Hong, C. Park, D. Kim, K.-S. Jeong, J.-S. Yoon, B. Jin, and J.-S. Lee, “Effect of surface functional groups on the pH sensitivity in ion-sensitive field effect transistors,” IEEE International Conference on Nanotechnology, Sendai, Japan, Aug. 2016.

  20. (Invited) J.-S. Yoon, S. Lee, S. Yoon, K. Kim, T. Rim, and C.-K. Baek, “Simulation and characterization of electronic and photonic devices using silicon nanowire structure,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Hakodate, Japan, Jul. 2016.

  21. J.-S. Yoon, E.-Y. Jeong, S.-H. Lee, Y.-R. Kim, J.-H. Hong, J.-S. Lee, and Y.-H. Jeong, “Extraction of source/drain series resistance components optimized for double-gate FinFETs,” International Conference on Solid-State Devices and Materials, Tsukuba, Japan, Sep. 2014.

  22. J. H. Hong, S. H. Lee, Y. R. Kim, E. Y. Jeong, J.-S. Yoon, J. S. Lee, R. H. Baek, and Y. H. Jeong, “Impact of high-k spacers on parasitic effects considering DC/AC performance optimization in Si-nanowire FETs for sub 10 nm technology node” International Conference on Solid State and Device Materials, Tsukuba, Japan, Sep. 8-11, 2014.

  23. S. H. Lee, Y. R. Kim, J. H. Hong, E. Y. Jeong, J. W. Jang, J.-S. Yoon, D. W. Kim, C. K. Baek, J. S. Lee, and Y. H. Jeong, “Characterization of low frequency noise in nanowire FETs considering variability and quantum effects,” IEEE Device Research Conference, Norte Dame, USA, Jun. 23-26, 2013, pp. 123-124.

  24. C. H. Park, M. D. Ko, K. H. Kim, J. H. Hong, R. H. Baek, J.-S. Yoon, J. S. Lee, and Y. H. Jeong, “Extraction of series resistance on junctionless and inversion-mode nanowire FET through the method based on Y-function,” IEEE Device Research Conference, Norte Dame, USA, Jun. 23-26, 2013, pp. 225-226.

Korea Conferences

• 1. K. Cho, H. Yun, H. Jang, K. Nam, C. Park, J.-S. Yoon, H.-C. Choi, and R.-H. Baek, "Improving program efficiency of 3D NAND cell structure based on artificial neural network," IEIE Summer Conference, Jeju, Korea, Jul. 2021. (Best Paper Award)

  2. J. Lee, J.-S. Yoon, S. Lee, J. Jeong, and R.-H. Baek, "Power, performance, and area analysis of source/drain patterning n/p FinFETs based 6T-SRAM cell for 3-nm technology node," Korean Conference on Semiconductors, Jeongseon, Korea, Feb. 2020. 

  3. K. Nam, C. Park, J.-S. Yoon, H.-D. Jang, and R.-H. Baek, "The origin of incremental step pulse programming (ISPP) slope degradation in NAND flash memory," Korean Conference on Semiconductors, Jeongseon, Korea, Feb. 2020. 

  4. S. Lee, J.-S. Yoon, J. Jeong, and R.-H. Baek, “Observation of mobility and velocity behaviors in ultra scaled Lg=15 nm silicon nanowire pMOSFETs with different channel diameters,” Korean Conference on Semiconductors, Heongsung, Korea, Feb. 2019. 

  5. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, “Threshold voltage variation induced by source/drain mole fraction and Si/SiGe intermixing of silicon nanosheet field-effect transistors,” Korean Conference on Semiconductors, Heongsung, Korea, Feb. 2019.

  6. S. Lee, J. Jeong, J.-S. Yoon, and R.-H. Baek, “Observation of mobility and velocity as channel diameter change in the shrunk Lg = 18nm silicon nanowire MOSFETs,” The Institute of Semiconductor Engineers, Pankyo, Korea, Dec. 2018.

  7. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek, “Geometric optimization of silicon gate-all-around field-effect transistors (GAAFETs) for DC/AC performances,” The Institute of Semiconductor Engineers, Pankyo, Korea, Dec. 2018. 

  8. S. Lee, K. Kim, J.-S. Yoon, and C.-K. Baek, “Differential 3w method for measuring thermal conductivity of silicon nanowire,” Korean Conference on Semiconductors, Hongcheon, Korea, Feb. 2017.

  9. W. Jeong, J.-S. Yoon, K. Kim, and C.-K. Baek, “Gas sensitivity variation with different defect density and dimensions in single ZnO nanowire gas sensor,” Korean Conference on Semiconductors, Hongcheon, Korea, Feb. 2017.

  10. S. Yoon, K. Kim, J.-S. Yoon, and C.-K. Baek, “The investigation of the responsivity on silicon photodetector depend on deposition technique: LPCVD vs. UHVCVD,” Korean Conference on Semiconductors, Hongcheon, Korea, Feb. 2017.

  11. J. Choi, J.-S. Yoon, K. Kim, and C.-K. Baek, “DC characteristics in polysilicon nanowire tunneling field-effect transistors,” Korean Conference on Semiconductors, Hongcheon, Korea, Feb. 2017.

Other (Korean, PCT, Taiwan) Patents

• 1. R.-H. Baek, J. Jeong, and J.-S. Yoon, "Gate-all-around field-effect transistor with trench inner-spacer and manufacturing method thereof," Korea Patent (Granted), 10-2543931, 2023.  (Technology Transfer)

  2. R.-H. Baek, J. Jeong, and J.-S. Yoon, “Gate-all-around field-effect transistor with trench inner-spacer and fabrication method thereof,” Taiwanese Patent (Filed), 111146434, 2022.  (Technology Transfer)

  3. R.-H. Baek, J. Jeong, and J.-S. Yoon, “Gate-all-around field-effect transistor with trench inner-spacer and fabrication method thereof,” PCT Patent (Filed), PCT/KR2022/006837, 2022.  (Technology Transfer)

  4. R.-H. Baek, J. Lee, and J.-S. Yoon, “Monolithic three-dimensional semiconductor integrated circuit device and fabrication method thereof,” Korea Patent (Granted), 10-2587997, 2023. 

  5. R.-H. Baek and J.-S. Yoon, “Single structure CASCODE device and fabrication method thereof,” Korea Patent (Granted), 10-2394193, 2022. 

  6. H.-C. Choi, R.-H. Baek, J.-S. Yoon, and H. Yun, “Semiconductor manufacturing parameter setting method and computing device for performing the same,” Korea Patent (Filed), 10-2020-0133780, 2020. 

  7. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Field-effect transistor with size-reduced source/drain epitaxy and fabrication method thereof,” Korea Patent (Granted), 10-2183131, 2020.

  8. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Field-effect transistor without punch-through stopper and fabrication method thereof,” Korea Patent (Granted), 10-2133208, 2020.

  9. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Metal source/drain-based metal-oxide-semiconductor field-effect transistor and method for fabricating the same,” Korea Patent (Granted), 10-2088706, 2020.  (Technology Transfer)

US Patents

• 1. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Field-effect transistor without punch-through stopper and fabrication method thereof,” US Patent (Granted), US 11,387,317, Jul. 2022.

  2. H.-C. Choi, R.-H. Baek, J.-S. Yoon, and H. Yun, “Method for setting of semiconductor manufacturing parameter and computing device for executing the method,” US Patent (Filed), 17/551,450, 2021.

  3. R.-H. Baek and J.-S. Yoon, "Single structure CASCODE device and fabrication method thereof," US Patent (Filed), 17/387,876, 2021.

  4. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, "Field-effect transistor with size-reduced source/drain epitaxy and fabrication method thereof," US Patent (Filed), 16/898,706, 2020.

  5. R.-H. Baek, J.-S. Yoon, J. Jeong, and S. Lee, “Metal source/drain-based metal-oxide-semiconductor field-effect transistor and method for fabricating the same,” US Patent (Filed), 16/562,693, 2019.  (Technology Transfer)

Book Chapters

• 1. R.-H. Baek and J.-S. Yoon, "Chapter 5: Characterization of Silicon FinFETs under nanoscale dimension," in Semiconductor and Technologies for Future Ultra Low Power Electronics, Taylor & Francis, London, United Kingdom: Informa UK Limited. 2021.

  2. J.-S. Yoon, J. Jeong, S. Lee, J. Lee, and R.-H. Baek, "Gate-all-around FETs - nanosheet structure," in Nanowires - Recent Progress, 5 princes Gate Court, London, United Kingdom: IntechOpen Limited. 2020.

  3. J.-S. Yoon and R.-H. Baek. "DC performance variations of SOI FinFETs with different silicide thickness," in Prime Archives in Physics, Hyderabad, India: Vide Leaf. 2020.