Failure moves you one step closer to the success

Hi, I'm Junaid Jalal
Fresh graduate, EEE, BUET

I have currently completed my Bachelor's degree in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology.
My research interest includes : Spintronics, VLSI, Topological insulators, Embedded systems, Solid State Devices, Digital Electronics.

Resume

Research Experience

Undergraduate Thesis: True Random Number Generator using VCMA Magnetic Tunnel Junction and LFSR Architecture (June 2024 - March 2025)

Supervisor : Dr. A. B. M. Harun-Ur-Rashid, Professor & Head, Department of EEE, BUET

This work explores stochastic behavior of MTJ to introduce random number generation in linear feedback shift register. It has developed an optimized feedback shift register using MTJ for generating random bits. The design has successfully passed NIST statistical test suit.

Achievements

Champion in analog domain of "VLSITHON 2.0 Battle of Analog and RTL Engineers "

This is a competition organized by Ulkasemi Pvt. Limited focusing on VLSI design of both analog and RTL domain. Competitive designing problems with specifications were given to solve in a fixed time duration. I along with my team "Helikopter" participated and became champion in analog domain.

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