Research

In applications where firmware updates are frequent, such as edge devices in the Internet of Things (IoT) networks with embedded systems, the update process is considered a significant role in improving device performance. This research proposed a user-insensible sliding firmware update technique based on a function block that reduces flash memory usage by handling only part of function blocks instead of the entire firmware, and the device's pause time by allowing the user to use the device between function block updates. The proposed technique was evaluated using the target board with the actual ARM core. We show that user-insensible sliding firmware update has great potential for implementing IoT networks that change behavior quickly by being aware of the environment. 

My research interests in AI on the embedded system by hardware & software co-design for lightweight edge AI. Typical inference requires only read operation to access static pre-trained weight parameters. On the other hand, training needs to use both read and write operations to update weight during backpropagation. In the case of MCU, on-device training faces two challenges; low-cost read-write accessible on-chip SRAM is too small to store the weight, and the relatively large flash memory has a write access constraint. Furthermore, considering conventional network size, flash memory is inevitable to realize on-device training on tiny MCU. To cope with the MCU memory constraints, we need to design AI software algorithms considering MCU hardware characteristics. We propose the gradient delta-based runtime adaptive partial update for weight stored in a flash memory according to the MCU's memory structure. Based on column-wise gradient delta computation at the training runtime, the weight to update is partially copied to SRAM from the flash memory-specific page. 

Iterative register-transfer level (RTL) simulation is essential for the edge processor design, but the RTL simulation speed is significantly slower in a system where various RTL models are complicatedly integrated. In this paper, we propose a novel metamorphic edge processor simulation framework that partitions the software part and virtualizes it in the system emulator to eject from full RTL simulation. The system emulator, which is written in a high-level language, and the Verilog simulation have different abstraction levels, thus the Verilog procedural interface (VPI) module is plugged into the Verilog simulator to connect with the virtual layer interface. In the system emulator, a Verilog RTL simulation session corresponding to a specific parameter set can be dynamically loaded at runtime to provide metamorphism by flexible partial parameter-driven RTL model replacement.