[2020-09-01] Reviewed the syllabus and created a Google site with a link to a GitHub repository.
[2020-09-03] Further reviewed the syllabus, introduced to VHDL (Chapter 1), and learned about basic VHDL rules like case sensitivity and sensitivity to white space (Chapter 2)
[2020-09-08] Learned more about VHDL architecture (comparison to a "black box"), and further reviewed VHDL language.
[2020-09-10] Downloaded Linux, GHDL, GtkWave, learned more about VHDL syntax, and finished up the last of the concurrent information of the textbook.
[2020-09-15] Ran "Hello World" program using GHDL, covered Data-flow/Behavorial Architecture and learned about VHDL Process and Sequential Statements (Chapter 5).
[2020-09-17] Created groups for future projects, learned about VHDL operators (Chapter 6) and went more in dept about sequential circuits (memory and storage elements; Chapter 7)
[2020-09-22] Learned more about Finite State Machine Design within VHDL (Chapter 8), while connecting FSMD to real life designs (heating systems, calculators, trains, etc.) The connection allowed me to visualize how a FSMD works within VHDL.
[2020-09-24] Reviewed other students' weekly reports and took note on how to improve my own weekly reports moving forward.
[2020-10-01] Caught up on reading chapter 9,10. Got ahead on going over chapter 11. Created a groupchat with my project group (FPGA <3).
[2020-10-06] Got ahead on reading chapter 12 (Looping Constructs). Took extra time to look at next and exit statements.
[2020-10-13] Finished the textbook by reading over Chapter 13 (Last chapter).
[2020-10-20] Started working on the labs with Lab 1. Looked at class recordings to aid in completing the lab.
[2020-10-22] Continued working on the labs with Lab 2. Looked at class recordings to aid in completing the lab.
[2020-10-27] Continued working on the labs with Lab 3. Looked at class recordings to aid in completing the lab.
[2020-10-29] Continued working on the labs with Lab 4. Looked at class recordings to aid in completing the lab.
[2020-11-03] Got together with the Lab Group and decided on what project we wanted to do. We decided on the Brick Breaker game.
[2020-11-05] Continued working on the labs with Lab 5. Looked at class recordings to aid in completing the lab.
[2020-11-10] Finished the labs by completing Lab 6. Looked at class recordings to aid in completing the lab.
[2020-11-19] Met with Group 5 to discuss the Final Project: Break Breaker. Found an existing project that was very similar from Rutgers (used a different board and languages) that used the same concept that we were looking for.
[2020-11-24] Met with Group 5 to further work on the Final Project and figured out how to write VHDL code to draw bricks onto the screen.
[2020-12-03] Finished our Final Project by writing VHDL code to detect collisions and make the bricks disappear; tested, debugged, and commented the code; created a website for our final project containing information and documentation (pictures and videos) with the group.
[2020-12-09] Worked on personal website by making it cleaner and user friendly. Updated weekly reports and contributions, and inserted a link to our group's final project website.
[2020-12-10] Finished up personal website by taking care of minor details/adding links. Edited class repo by uploading previous worked on codes for all the labs (edits to lab code can be found in README.md) and our final project.