ACHIEVEMENTS

• S.- W. Oh, D.-R. Oh, "Two-rank Decimation Technique for High-speed Time-interleaved Analog-to-digital Converters", Journal of Semiconductor Technology and Science(JSTS), vol. 25, no. 3, Jun. 2025.

• D.- Y. Kim, S.- W. Oh, H.-G. Hwang, Y.- S. Kim, D.-R. Oh, "Loop-unrolled SAR ADC with complementary voltage-to-time converters", in The Institution of Engineering and Technology(IET), Lett., 61: e70242, April. 2025

• B.-J. Kim and D.-R. Oh*, "Power-efficient 4-bit 40-MS/s Time-domain 2-times Interpolating Flash ADC Using Complementary Latching Technique", in International Journal on Advanced Science Engineering Information Technology(IJASEIT), vol. 14, no. 6, Dec. 2024.

• K. E. Lozada, D. -J. Chang, D. -R. Oh, M. -J. Seo and S. -T. Ryu, "SAR-Assisted Energy-Efficient Hybrid ADCs," in IEEE Open Journal of the Solid-State Circuits Society(OJ-SSCS), vol. 4, pp. 163-175, 2024.

• J.-H. Chung, Y.-D. Kim, C.-U. Park, K.-W. Park, D.-R. Oh, M.-J. Seo*, and S.-T. Ryu*, " A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC",  IEEE J. Solid-State Circuits (JSSC), vol. 59, no. 8, Aug. 2024. 

• D.-R. Oh*, “A 6-bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS,” MDPI Electronics, vol. 11, no. 19, Sep. 2022.

• D.-R. Oh, M.-J. Seo and S.-T. Ryu*, “A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique,” IEEE J. Solid-State Circuits (JSSC), vol. 57, no. 9, pp. 2791-2801, Sep. 2022.

• E.-J. An and D.-R. Oh*, “A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS,” MDPI Electronics, vol. 11, no. 11, May 2022.

• D.-R. Oh, K.-J. Moon, W.-M. Lim, Y.-D. Kim, E.-J. An, and S.-T. Ryu*, “An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 56, no. 4, pp. 1216-1226, Apr. 2021.

• K.-J. Moon, D.-R. Oh, M. Choi and S.-T. Ryu*, “A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC,” IEEE Trans. Circuits and Systems II (TCAS II), vol. 67, no. 12, pp. 2843-2847, Dec. 2020.

• D.-R. Oh, J.-I. Kim, D.-S. Jo, W.-C. Kim, D.-J. C. and S.-T. Ryu*, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration,” IEEE J. Solid-State Circuits (JSSC), vol. 54, no. 1, pp. 288-297, Jan. 2019.

• D.-R. Oh, D.-S. Jo, K.-J. Moon, Y.-J. Roh and S.-T. Ryu*, “Power-efficient flash ADC with complementary voltage-to-time converter,” IET Electronics Letters (EL), vol. 53, no. 12, pp. 772-773, Jun. 2017.

• J.-I. Kim, D.-R. Oh, D.-S. Jo, B.-R.-S. Sung, and S.-T. Ryu*, “A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation,” IEEE J. Solid-State Circuits (JSSC), vol. 50, no. 10, pp. 2319-2330, Oct. 2015.

Patents

• (US) K.-J. Moon, D.-R. Oh, Y.-J. Jo, M. Choi, “ANALOG-TO-DIGITAL CONVERTER,” 11190202, 2021-11-30. (한국; app. No.: 1020200007273)

• (US) K.-H. Kim, D.-R. Oh, S.-T. Ryu, “ANALOG-TO-DIGITAL CONVERTER AND SEMICOND UCTOR MEMORY DEVICE HAVING THE SAME,” 11133816, 2021-09-28. (CN; app. No.: 202011410358.3, KR; app. No.: 1020200036062)

• (KR) 류승탁, 오동렬, “샘플앤홀드 공유에 기반하는 2단 플래시 ADC,” 102199016, 2020-12-30.

• (KR) 류승탁, 오동렬, “오프셋 보정이 적용된 아날로그-디지털 데이터 변환기 및 보정방법,” 101836222, 2018-03-02.

• (KR) 류승탁, 오동렬, “시간 영역 다단 인터폴레이션 기법을 이용한 저전력 아날로그 디지털 변환기,” 101644999, 2016-07-27.

Applications

• (KR) 오동렬, "고속 시간 분할 ADC 데시메이션 시스템 및 방법", 10-2024-0044688, 2024-04-02.

• (KR) 오동렬, "상보 증폭기를 이용한 루프-언롤드 SAR ADC 시스템," 10-2024-0041580, 2024-03-27.

• (KR) 오동렬, 김범진, "상보 증폭기를 이용한 인터폴레이팅 Flash ADC," 10-2023-0174253, 2023-12-05.

• (KR) 오동렬, 이재강, "상보 증폭기를 이용한 연속근사레지스터 데이터 변환기," 10-2023-0174265, 2023-12-05.

• (KR) 오동렬, "위상 인터폴레이션 기반 시간영역 8배 인터폴레이팅 플래시 아날로그 디지털 컨버터의 선형성 개선시스템," 10-2023-0079154, 2023-06-20.

• (US) K.-J. Moon, D.-R. Oh, Y.-H. Park, Y.-J. Cho, M. Choi, “ANALOG-TO-DIGITAL CONVERTER,” 17406193, 2021-08-19. (한국; app. No. 1020200175437)

• (KR) 류승탁, 오동렬, “다중 비트 다단 2진 검색 아날로그-디지털 변환기,” 10-2018-0011548, 2018-01-30.

International

• K.-J. Moon, D.-R. Oh, Y.-H. Park, K.-H. Lee, S.-J. Park, S.-N. Lee, H.-C. Hwang, H.-C. Shin, Y.-J. Cho, M. Choi, and J.-S. Shin, “A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET,” in IEEE Symp. VLSI Circuits, Jun. 2022.

• D.-R. Oh, K.-J. Moon, W.-M. Lim, Y.-D. Kim, E.-J. An and S.-T. Ryu, “An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers,” in IEEE Symp. VLSI Circuits, Jun. 2020 (Invited to special issue of IEEE JSSC).

• D.-R. Oh, J.-I. Kim, M.-J. Seo, J.-G. Kim and S.-T. Ryu, “A 6-bit 10-GS/s 63-mW 4x TI Time-Domain Interpolating Flash ADC in 65-nm CMOS,” in IEEE European Solid-State Circuits Conf., Sep. 2015.

Domestic

• Jae-kang Lee, Da-yeon Kim, hyeon-gi Hwang, Sang-won Oh, Dong-ryeol Oh, "A 6 bits 1 MS/s SAR ADC with a high power-efficiency Complementary dynamic amplifier", IEIE RF/아날로그 워크샵, 26 Sep. 2024. (RF 집적회로 연구회 우수논문상)

• Beom-Jin Kim, Jae-Kang Lee, Han-Jun Kim, Sang-Won Oh, Hyeon-Gi Hwang, Da-Yeon Kim, Ye-Won Yun, and Dong-Ryeol Oh, "A 2-times time-domain interpolating Flash ADC with complementary dynamic amplifier", IEIE RF/아날로그 워크샵, 26 Sep. 2024.

• HanJun Kim, WoongKi Yang, YuSeong Kim, DongRyeol Oh, "An Efficient 4x Time-Domain Interpolating Flash ADC utilizing Complementary Dynamic Amplifiers", IEIE RF/아날로그 워크샵, 26 Sep. 2024. (기업특별상-키사이트테크놀로지스)

• Da-yeon Kim, Hyeon-gi Hwang, Sang-won Oh, Dong-ryeol Oh, "Bidirectional Dynamic Amplifiers for 6-Bit 10 MS/s Asynchronous Loop-Unrolled SAR ADC", IEIE RF/아날로그 워크샵, 26 Sep. 2024.

• 김다연, 오상원, 황현기, 오동렬, "A 6 bits 10 MS/s Asynchronous Loop-Unrolled SAR ADC", IEIE 하계학술대회, 26 Jun. 2024.

• 김한준, 양웅기, 김유승, 오동렬, "상보 동적 증폭기 기반 4배 시간 영역 인터폴레이팅 Flash ADC", IEIE 하계학술대회, 26 Jun. 2024.

• Jae-kang Lee, Beom-Jin Kim, Da-yeon Kim, Hyeon-gi Hwang, Sang-won Oh, Dong-ryeol Oh, "A 6 bits 1 MS/s SAR ADC with a power-efficient Complementary dynamic amplifier", IEIE 하계학술대회, 26 Jun. 2024.

• Beomjin Kim, Jaekang Lee, Hanjun Kim, Yewon Yun, Dongryeol Oh, "A 2-times time-domain interpolating Flash ADC with complementary dynamic amplifier", IEIE 하계학술대회, 26 Jun. 2024.

• 이재강, 김다연, 황현기, 오상원, 오동렬, "A 6 bits 5 MS/s SAR ADC with a high-efficiency Complementary dynamic amplifier", IEIE CEIC, 7 Dec. 2023.

• 김범진, 양웅기, 김한준, 김유승, 오동렬, "Power-efficient flash ADC with complementary dynamic amplifier and 2-times time-domain interpolating", IEIE CEIC, 7 Dec. 2023.

• 이재강, 김범진, 오동렬, "위상 인터폴레이션 기반 시간 영역 8배 인터폴레이팅 Flash ADC의 선형성 개선 방법," IEIE 하계학술대회, 28 Jun. 2023.