COVID-19 Projects

Project - 1

Diagnosis of COVID-19 using ADAM Optimization technique in Convolutional Neural Network (CNN)

The new COVID-19 has range promptly among people and is approaching roughly 34,986,502 cases global, as stated in the data of the European Centre for Disease Inhibition and Control. There is an undersupplied quantity of COVID-19 testing equipment offered in hospitals as a consequence of the cumulative cases every day. Consequently, it is essential to carry out a spontaneous disclosure system as a rapid alternate prognosis possibility to avert COVID-19 from spreading among people. In this paper, a novel CNN architecture has been proposed to enhance the accuracy expectation of COVID-19 elicited from chest X-ray input resemblance since the vast majority of the positive cases are recognized by taking the chest radiographs. The training process required datasets for machine learning classifiers. The datasets (1576 healthy, 3546 Pneumonia, and 289 confirmed COVID-19) have been taken from the authorized scanning center. The suggested model can attain better accurate results with less training time of data. Inclusively, the proposed model extensively developments the existing roentgenology procedure. For the period of COVID- 19 widespread, it can be a beneficial tool for medical specialists and radiographers to diagnose, quantify, and explore COVID-19 cases.

Project - 2

IoT Based Smart Door System to prevent COVID-19 Virus

Recently, the world is struggling with the Coronavirus. It affects our daily routine life and global economy. It is considered a huge challenge to avoid the dissemination of the virus among people. Even though many countries are employed certain relaxation with restrictions, the outspread is not over yet. Thereby following the social distance is the only solution to avoid COVID-19. To assist with this, smart devices are the best choice to prevent coronavirus spread. The smart devices acting as a primary role in the new-fangled normal world will function from now onwards. This paper proposes a resolution for circumventing suspicious persons with Corona symptoms based on an IoT system. In this work, my device's Cayenne open-source framework has been employed for the IoT-cloud module. This framework provides efficient interconnection between smart devices, preparing them with intelligence that benefits mechanizing the door system. The IoT platform Cayenne is constructed on ESP8266 chips, Raspberry Pi boards, Arduino boards, and smart sensors. It is in the form of a mobile application that consents operators to regulate a sequence of utilizations and sensors.

Guided Projects (17 Batch)

Team - 1

IoT Based Smart Door System to prevent COVID-19 Virus

Recently, the world is struggling with the Coronavirus. It affects our daily routine life and global economy. It is considered a huge challenge to avoid the dissemination of the virus among people. Even though many countries are employed certain relaxation with restrictions, the outspread is not over yet. Thereby following the social distance is the only solution to avoid COVID-19. To assist with this, smart devices are the best choice to prevent coronavirus spread. The smart devices acting as a primary role in the new-fangled normal world will function from now onwards. This paper proposes a resolution for circumventing suspicious persons with Corona symptoms based on an IoT system. In this work, my device's Cayenne open-source framework has been employed for the IoT-cloud module. This framework provides efficient interconnection between smart devices, preparing them with intelligence that benefits mechanizing the door system. The IoT platform Cayenne is constructed on ESP8266 chips, Raspberry Pi boards, Arduino boards, and smart sensors. It is in the form of a mobile application that consents operators to regulate a sequence of utilizations and sensors.

Team- 2

Comparative analysis of SRAM using 14nm FinFET Technology

Electronic manufacturing markets focus on the miniaturization of existing devices and deliver products in smaller sizes with higher speeds and power efficiencies. The current transistor technology uses planar CMOS transistors, which are used for many analog and digital applications. According to Moore’s law, the number of transistors in an area should double every 18 months. For this to happen, transistors should shrink in size to accommodate double the number per same unit area. Unfortunately, CMOS has short channel effects and leakage coming into the picture when its gate length is reduced and cannot be put into use beyond 22nm reduction. To replace nano-scale CMOS, a double-gate device called FinFETs is used. FinFETs proved to be better efficient in performance than CMOS. In this project, SRAM is designed in FinFET 14 nm technology and analyzes the power dissipation.

Team- 3

DESIGN AND ANALYSIS OF FIR FILTER USING HADAMARD TRANSFORM

Design and analysis of FIR filter for image compression and decompression application using Hadamard transform. Image compression encodes digital image information using fewer bits than an unencoded representation would use to use specific encoding schemes. Decompression is the process of restoring compressed data to its original form. Data decompression is required in almost all cases of compressed data, including loss and lossless compression. The image compression will be performed by the efficient technique called the HADAMARD TRANSFORM. The decompression image is performed by inverse Hadamard transform. Then analyze the compressed image size and PSNR ratio of the compressed image. The intoned to design a novel technique for the practical compression application.

Doctor of Philosophy

ABSTRACT

The Digital Signal Processor is an inevitable element for real-time applications in VLSI, and the Multiply-Accumulate unit plays quite a significant role in the Digital Signal Processing applications such as filtering, Fast Fourier Transform, and Discrete Cosine Transform. Although Moore's law reduces hardware complexity and computation, it leads to higher power consumption. The multiplier is the core of the DSP processor, which is responsible for the hardware complexity. When the size of the multiplier is reduced, there is a marked reduction in power consumption, which is realized with the application of a Fixed-width multiplier because of its specific features. The name 'Fixed-width' denotes that the multiplier has a fixed width in its output bits; therefore, the output bits are the same as the input bits. Since the Fixed-width multiplier eliminates most of the LSB bits, thereby it saves the multiplier circuit area. With fewer full adders, the computation became more comfortable with lower power consumption. The challenge of the Fixed-width multiplier design is to attain maximum accuracy in the output with the reduction of the bits. The error compensating circuit has to be constructed to nullify the error in the circuit.

This thesis makes an effort to present a new approach to design the Fixed-width multiplier for both high-speed and low-power, without sacrificing the accuracy for the Floating-point computation. Most of the DSP applications, such as filtering, require Floating-point arithmetic for achieving accuracy. This research brings forth a practical algorithm for the Fixed-width multiplication with a refined accurateness for the Floating-point application.

The first approach is to use an RLNS (Residue and Logarithmic Number System) algorithm, with a combination of both RNS and LNS. The RNS number system has three intriguing properties. Initially, as it did not need to carry propagation, it realized high-speed and low-power computation. Secondly, since the Residue Number System did not contain any weight information, the error occurring in any position did not affect other positions of the bits. Lastly, no significant order was discovered in the digits to discard the faulty bits. Some applications regarding the usage of RNS, are digital to analog converter, FIR filter, Adaptive filter, 2D FIR filter, and digital frequency synthesis. The effective use of the Logarithmic Number System is used to represent the data of the special-purpose processors. The salient feature of the LNS is to restrict the arithmetic operations such as multiplication, division, square root, and the square to a minimum binary addition and subtractions. The RLNS algorithm is strategically used to design a high-performance system in Digital Signal Processing by enhancing the processing speed and bringing down the power consumption. The Residue Number System gets involved by converting decimal to residue system and vice versa.

The correct selection of the module is highly responsible for the conversion from the Decimal to the Residue Number System. The Chinese Remainder Theorem or the Mixed Radix Conversion is used for retrieving the Decimal Number from the Residue Number System. The Residue Number System is suited for the Fixed-point number, which typifies real and imaginary numbers. Quick multiplication and division occurs in the Logarithmic Number System and is found to be more precise in the Floating-point calculations. As a result, the synthesis of the RNS and LNS algorithm work out both the Fixed and Floating point computations, executed in the Fixed-width multiplier. The error is compensated by the Taylor series expansion. The accuracy level of the proposed Fixed-width multiplier can be augmented with an accretion of the 'nth' terms in the Taylor series. To retrieve the accuracy, the number of terms in the expansion has to be marked up. The second approach uses a novel modified Floating-point Radix-4 algorithm. The Booth multiplier offers very fast multiplication by recoding the multiplier bits. At the same time, the Radix-4 method provides less area and power consumption. In the present approach, a modified Floating-point Radix 4 algorithm has proposed to yield a high computation speed than the existing method. The intention of this proposed work is to reduce the computation time by reducing the number of multiplications and additions. The novel modified Floating-point Radix-4 algorithm is mainly apt for improving the processing speed. The Radix-4 only needs fewer stages of calculations compared to Radix-2. The accuracy of the proposed multiplier design can be enhanced by various rounding techniques.

The third approach uses a Column Bypassing Technique for the Fixed-width multiplier. This technique is used for accomplishing less power dissipation, which is realized by reducing the internal switching activity of the nodes. The Column bypassing technique reduces the switching activity by eliminating some of the columns of the multiplicand if zero. In literature, Full-width and Fixed-width multiplier has been designed only with bypassing technique for reducing power consumption and delay so far. However, in this proposed system, the Fixed-width multiplier is designed with Column bypassing algorithm, which is utilized for Floating-point computation. Moreover, the proposed work achieves better power reduction and also ensures accuracy.

This research work presents a novel technique for designing the Fixed-width multiplier using various methods such as Residue Logarithmic Number System, Radix -4, Column bypassing technique, and Reduced Precision Redundancy (RPR). The efficient error compensation function has been computed by Taylor series expansion, probability statistics, and various rounding techniques to improve their accuracy and to reduce the truncation error. The designed MAC unit is implemented in the FIR filter for performance evaluation. The comparative analysis of the proposed methods has been performed, and the simulation results investigate the best approach in terms of MAC and filter performance.

Master of Engineering

ABSTRACT

Electronic manufacturing markets focus on the miniaturization of existing devices and deliver products in smaller sizes with higher speeds and power efficiencies. The current transistor technology uses planar CMOS transistors, which are used for many analog and digital applications. According to Moore’s law, the number of transistors in an area should double every 18 months. For this to happen, transistors should shrink in size to accommodate double the number per same unit area. Unfortunately, CMOS has short channel effects and leakage coming into the picture when its gate length is reduced and cannot be put into use beyond 22nm reduction. To replace nano-scale CMOS, a double-gate device called FinFETs is used. FinFETs proved to be better efficient in performance than CMOS. In this project, for phase I Adder circuit is designed in CMOS and FinFET technology in 45 nm and compare its characteristics. And for phase II, the Arithmetic and Logic Unit is designed in FinFET 45 nm technology and analyzes the power dissipation.

Mini Project -1

Aim: To design an ALU circuit using Encounter digital flow (Cadence Virtuoso- Encounter to GDSII).

Abstract: The Encounter digital flow allows route the ALU circuit, such as local routing, area routing, channel routing, and global routing. Encounter flow used to determine time design summary, clock tree synthesize, LVS and DRC`. To create a path for power rings, floor planning will be done.

Mini Project -2

Aim: Design a 4×1 Multiplexer circuit using Encounter digital flow (Cadence Virtuoso- Encounter to GDSII).

Abstract: The Encounter digital flow allows route 4×1 Multiplexer circuit, such as local routing, area routing, channel routing, and global routing. To determine the time design summary, clock tree synthesize, LVS, and DRC encounter flow used. To create a path for power rings, floor planning will be done.

Bachelor of Technology

Title: Investigation of Nano-scale FinFETs for Memories

Abstract: To analyze the performance of FinFETs by using different types of materials in the gate. The device modeling is done with the help of Synopsys TCAD Software.