1. M.Tech. (Microelectronics and VLSI Design), Indian Institute of Science (2020-22)
GPA: 9.90/10 (3.96/4)
Thesis Title: Drain Extended High Voltage Devices for SoC Applications in Vertically Stacked Nanosheets Technology
Advisor: Prof. Mayank Shrivastava
2. B.Tech. (Electronics and Communication Engineering), Delhi Technological University (2015-19)
GPA: 9.90/10 (3.96/4)
Thesis Title: Metamutators: Study and novel realizations
Advisor: Prof. Neeta Pandey
1.Analog Design Engineer, Analog Devices (Aug 2022-Present)
Working in the BMS Group for the design of the next Gen. Wireless TRx for automotive applications.
Blocks: Phase Locked Loops, Analog to Digital Converters, RF Power Detectors
2. Mixed Signal Design Engineer, Samsung Semiconductors (Jun 2019- Aug 20)
Worked in the eNVM Team of the Foundry division for the design and verification of OTP Memory IPs.
Blocks: LDOs, Current Reference Generators