Contact Info
+91- 9717522675
I am an RFIC/Analog Design Engineer at Analog Devices. My research interests include RF ICs, Analog Circuit Design, and Electrostatic-Discharge (ESD) protection device design.
I received my B.Tech. Degree in Electronics & Communication Engineering from Delhi Technological University (Delhi, India) in 2019, and my M.Tech. Degree in Microelectronics and VLSI Design from the Indian Institute of Science (Bangalore, India) in 2022.
During my master's degree, I was lucky to have been a member of the Advanced Nanoelectronics Device and Circuit Research Group, supervised by Prof. Mayank Shrivastava. My thesis is titled "Drain Extended High Voltage Devices for SoC Applications in Vertically Stacked Nanosheets Technology."
From June 2019 to August 2020, I was with the eNVM Design team at Samsung Semiconductors (Bangalore, India), where I was involved in the design and verification of OTP memory IPs. The work involved the design of analog blocks, including voltage regulators, current references, and their digital control blocks.
I was awarded the Chancellor's Gold Medal in 2019, Employee of the Month (Samsung Semiconductors) in November 2019, and have secured Rank 1 in my masters (Batch 2020-22).
January 2023 - Accepted paper in IEEE IRPS Conference 2023 (Monterey, CA, USA)
December 2022 - Two accepted papers in IEEE ICEE Conference 2022 (Bangalore, INDIA)
August 2022 - Joined Analog Devices as an Analog Design Engineer
June 2022 - Graduated from Indian Institute of Science