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My Digital Logic Design course covers Boolean algebra, logic simplification, combinational logic (decoders, multiplexers), sequential logic (flip-flops, counters), and programmable logic devices (PLDs) using a Hardware Description Language.
My Digital Logic Design course covers Boolean algebra, logic simplification, combinational logic (decoders, multiplexers), sequential logic (flip-flops, counters), and programmable logic devices (PLDs) using a Hardware Description Language.
Our lab assignments reinforced concepts using microcontrollers and industry-standard tools, by focusing on designing complex digital systems from fundamentals to practical application. For the final project the class was split into groups with each using the skills we learned to create a design to simulate a Traffic Light Circuit.
Our lab assignments reinforced concepts using microcontrollers and industry-standard tools, by focusing on designing complex digital systems from fundamentals to practical application. For the final project the class was split into groups with each using the skills we learned to create a design to simulate a Traffic Light Circuit.
Project Description
Project Description
The goal of this project was to design and build a simulation of a traffic light system for the intersection of Highway 120 and the Miller Parkway. The traffic light system is intended to perform the following functions: count the number of cars waiting at Miller Parkway and Highway 120 and correctly cycle through the traffic light states (green, yellow, red)
The default state is green on 120 Highway and red on Miller Parkway. Stay true while Tg.
When a vehicle is sensed, Vs= true and Tg= false we enter the next state: yellow on 120 and red on Miller Parkway.
The machine enters the next state when Ty=false, and Vs=true we enter the next state: red 120 and green Miller Parkway.
The machine enters the next state when Tg=false, we enter the next state: red 120 and yellow Miller Parkway.
The machine enters back to the default state when Ty=false, green 120, and red Miller Parkway.
Diagram Sketches
Diagram Sketches
Gal22v10 Chip
Gal22v10 Chip
The GAL22V10 is a programmable logic device developed by Lattice Semiconductor. Aside from programmable pins, this device features various combinational logic gates: such as: AND, OR, NOT(Inverter), NAND (NOT-AND), NOR (NOT-OR), XOR (Exclusive OR), XNOR (Exclusive NOT-OR).
VHDL Code for 22v10 encoder
VHDL Code for 22v10 encoder
-- Crimm's template for State Machines using VHDL and a 22v10
library ieee;
use ieee.std_logic_1164.all;
entity TrafficLightGroup1 is
port(Tg, Ty, Vs, CLK:in std_logic; Q:buffer std_logic_vector (0 to 5));
end entity TrafficLightGroup1;
architecture StateMachine of TrafficLightGroup1 is
begin
process (Tg, Ty, Vs, CLK)
begin
if CLK = '1' and CLK'event then
case Q is
when "000000" => Q <="110011";
when "110011" => if
Tg = '1' and Vs = '0' then Q‹="110011";
elsif
Tg = '0' and Vs ='1' then Q‹="101011";
end if;
when "101011" →> if
Ty = '1' then Q‹="101011";
elsif
Ty='0' then Q‹="011110" ;
end if;
when "011110" →> if
Tg = '1' and Vs = '0' then Q‹="011110";
elsif
Tg = '0' and Vs = '1' then Q‹= "011101";
end if;
when "011101" => if
Ty = '1' then Q‹="011101"; --Ymp R120
elsif
Ty = '0' then Q‹="110011";
end if;
when others => Q <= "110011";
end case;
end if;
end process;
end architecture StateMachine;
Additional Circuits
Additional Circuits
0-99 Decimal Counter
Hex Counter
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