Aggelos D. Ioannou
Publications
Publications
Books / Chapters
K. Georgopoulos, K. Bakanov, I. Mavroidis, I. Papaefstathiou, A. Ioannou, P. Malakonakis, K. Pham, D. Koch, L. Lavagno (2019). "A Novel Framework for Utilising Multi-FPGAs in HPC Systems", Chapter in Heterogeneity Alliance Book "Heterogeneous Computing Architectures", 2019
Books / Chapters
K. Georgopoulos, K. Bakanov, I. Mavroidis, I. Papaefstathiou, A. Ioannou, P. Malakonakis, K. Pham, D. Koch, L. Lavagno (2019). "A Novel Framework for Utilising Multi-FPGAs in HPC Systems", Chapter in Heterogeneity Alliance Book "Heterogeneous Computing Architectures", 2019
Invited Talks / Articles
A. Ioannou: invited talk on "Heterogeneous computing: the potential of seamlessly integrating FPGAs into future HPC systems", HIPEAC Computing Systems Week (CSW) Spring 2021, topic: "Future Generation Heterogeneous Computing", 13th April 2021
I. Mavroidis, A. Ioannou and K. Georgopoulos, invited article on “Injecting and managing accelerators: ECOSCALE (Energy-Efficient Heterogeneous Computing at Exascale)”, HiPEACinfo magazine, October 2017
Journal Papers
P. Malakonakis, G. Isotton, P. Miliadis, C. Alverti, D. Theodoropoulos, D. Pnevmatikatos, A. Ioannou, K. Harteros, K. Georgopoulos, I. Papaefstathiou, I. Mavroidis, "Preconditioned Conjugate Gradient Acceleration on FPGA-Based Platforms", Electronics 2022, 11, 3039
A. Ioannou, K. Georgopoulos, P. Malakonakis, D. Pnevmatikatos, V. Papaefstathiou, I. Papaefstathiou, I. Mavroidis, “UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 13, Issue 4, September 2020
A. Ioannou and M. G. H. Katevenis, "Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks" in IEEE/ACM Transactions on Networking, vol. 15, no. 2, pp. 450-461, April 2007
Refereed Conference and Workshop Papers
M. Gianioudis et al., "Low-latency Communication in RISC-V Clusters", In Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region (HPCAsia '24), ACM, January 2024, Pages 73–83 (https://doi.org/10.1145/3635035.3635050)
D. Theodoropoulos et al., "Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project", 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-4, doi: 10.23919/DATE56975.2023.10136980
A. Biagioni, P. Cretaro et al.,"RED-SEA: Network Solution for Exascale Architectures", 25th Euromicro Conference on Digital System Design (DSD) 2022, Gran Canaria, Spain, August 31- September 3, 2022
K. Pham, D. Koch, A. Vaishnav, K. Georgopoulos, P. Malakonakis, A. Ioannou, I. Mavroidis, "Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O Virtualisation" 2020 International Conference on Field-Programmable Technology (ICFPT), 2020, pp. 221-226
F. Chaix, A. Ioannou, N. Kossifidis et al., "Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping," IEEE/ACM Heterogeneous High-performance Reconfigurable Computing (H2RC), Super Computing 2019, Denver, CO, USA, 2019, pp. 34-41
A. Ioannou, P. Malakonakis, K. Georgopoulos, I. Papaefstathiou, A. Dollas and I. Mavroidis: "Optimized FPGA Implementation of a Compute-Intensive Oil Reservoir Simulation Algorithm", 19th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July 7-11, 2019
G. Pitsis, G. Tsagkatakis, C. Kozanitis, I. Kalomoiris, A. Ioannou, A. Dollas, M. Katevenis, and P. Tsakalides, "Efficient Convolutional Neural Network Weight Compression for Space Data Classification on Multi-FPGA Platforms," in Proc. 44th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2019), Brighton, UK, May 12-17, 2019
I. Kalomoiris, G. Pitsis, G. Tsagkatakis, A. Ioannou, C. Kozanitis, A. Dollas, P.Tsakalides, M. Katevenis, “An Experimental Analysis of the Opportunities to Use Field Programmable Gate Array Multiprocessors for On-board Satellite Deep Learning Classification of Spectroscopic Observations from Future ESA Space Missions”, European Workshop on On-Board Data Processing (OBDP2019)
A. Ioannou, K. Georgopoulos, P. Malakonakis, I. Mavroidis, I. Papaefstathiou: "ECOSCALE – Towards HPC based on the UNILOGIC architecture and a novel interconnect/addressing scheme for global resource sharing", Towards European Exascale HPC Workshop at the HiPEAC’19 Conference, Valencia, Jan. 2019
F. Chaix, A. Ioannou, N. Kossifidis, M. Ligerakis, I, Mavroidis, M. Katevenis: "Experience on the ongoing Bring-up of ExaNeSt’s ZYNQ Ultrascale+ -based high density daughter board", Towards European Exascale HPC Workshop at the HiPEAC’19 Conference, Valencia, Jan. 2019
A. Ioannou, P. Malakonakis, K. Georgopoulos, I. Papaefstathiou, I. Mavroidis, A. Dollas: "FPGA accelerator optimizations for Diversified Oil Reservoir Simulation Algorithms", Contest winner in: International contest on Accelerated Heterogeneous Cloud Computing, organized within AccelCloud: Workshop and Contest on Accelerating Big Data in Heterogeneous Cloud computing, HiPEAC’19 Conference, Valencia, Jan. 2019
Y. Beilliard, M. Godard, A. Ioannou, A. Damianakis, M. Ligerakis, I. Mavroidis, P.-Y. Martinez, D. Danovitch, J. Sylvestre, D. Drouin: "FPGA-based Multi-Chip Module for High-Performance Computing - ExaNoDe", Towards European Exascale HPC Workshop at the HiPEAC’19 Conference, Valencia, Jan. 2019
P. Malakonakis, K. Georgopoulos, A. Ioannou, L. Lavagno, I. Papaefstathiou, I. Mavroidis, “HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware – ECOSCALE”, 14th International Symposium on Applied Reconfigurable Computing (ARC), May 2-4, 2018
K. Georgopoulos, A. Ioannou, P. Malakonakis, I. Mavroidis, V. Papaefstathiou, I. Sourdis, “UNIMEM and UNILOGIC architectures for local/remote sharing of resources”, ExascaleHPC Workshop, Manchester, Jan. 2018
V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, and M. Katevenis, "Prototyping Efficient Interprocessor Communication Mechanisms", Proc. IEEE International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS2007), 16-19 July 2007, Samos, Greece
V. Papaefstathiou, G. Kalokairinos, A. Ioannou, M. Papamichael, G. Mihelogiannakis, S. Kavadias, E. Vlahos, D. Pnevmatikatos and M. Katevenis, "An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication", In the 2nd HiPEAC Industrial Workshop on Embedded Computing, 17 October 2006, Philips (NXP) Eindhoven, Netherlands
A. Ioannou, T. Oikonomou and S. Diamantidis,"Multiple Interface Cross-Checking in a Single eVC Architecture",Club Verification 2003 - Verisity Users Group, Munich, Germany, March 3, 2003
A. Ioannou and M. Katevenis: "Pipelined heap (priority queue) management for advanced scheduling in high-speed networks". In the Proceedings of the IEEE International Conference on Communications (ICC'2001). Helsinki, Finland, June 2001, pp.2043-2047
Technical Reports
Aggelos D. Ioannou: "An ASIC Core for Pipelined Heap Management to Support Scheduling in High Speed Networks", Master of Science Thesis, University of Crete, Greece; Technical Report FORTH-ICS/TR-278, Inst. of Computer Science, FORTH, Heraklio, Crete, Greece, November 2000, 64 pages
George Kalokerinos, Vassilis Papaefstathiou, Angelos Ioannou, Manolis Marazakis, Angelos Bilas, and Manolis Katevenis, “Design and Implementation of a Multi-Gigabit NIC and a Scalable Buffered Crossbar Switch”, FORTH-ICS, Technical Report 376, Heraklion, Greece, April 2006.
Posters
I. Mavroidis et. al, "Accelerating real-world applications on novel multi-FPGA platforms", ISC High Performance 2022, May 29 - June 2, Congress Center Hamburg, Germany
A. Ioannou, I. Mavroidis, K. Harteros, G. Kalokerinos, A. Psathakis, M. Katevenis et al. 2016, “36-core, low power, exascale computing emulator based on 64-bit ARMv8 and Xilinx Ultrascale FPGAs”, ACACES 2016 Poster Abstracts, Fiuggi, Italy: HiPEAC High-Performance Embedded Architecture and Compilation (p. 11-14).
V. Papaefstathiou, G. Kalokairinos, A. Ioannou, M. Papamichael, G. Mihelogiannakis, S. Kavadias, E. Vlahos, D. Pnevmatikatos and M. Katevenis, "An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication", Poster presented at the 2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN2006), 6-7 December 2006, Stanford California, USA
Theses
Aggelos Ioannou, "UniLogic (Unified Logic): a scalable architecture for increased programmability in highly parallel reconfigurable systems", Doctoral Dissertation, School of Electrical and Computer Engineering, University of Crete, Chania, Greece, 2020
Aggelos Ioannou, "An ASIC Core for Pipelined Heap Management to Support Scheduling in High Speed Networks", M.Sc. Thesis (unfortunately in Greek. See the related Technical Report for a thorough description in English), Computer Science Department, University of Crete, Heraklion, Greece, 2000
"Aggelos Ioannou, Design of the Main Controller for the MuQProI Switch", B.Sc. Thesis, Computer Science Department, University of Crete, Heraklion, Greece, 2002 (check for a related publication)
Other Unrefereed
P. Malakonakis, K. Georgopoulos, A. Ioannou, L. Lavagno, I. Papaefstathiou and I. Mavroidis, “HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware”, PRACEdays18, European HPC Summit Week, May 2018