Intelligent Multi-Level Power-Aware Circuits and sysTems (IMPACT) Lab 

Over the past several years, Dr. Jinhui Wang has published 170+ peer-reviewed papers all in leading academic journals and conferences, here some selected refereed Journal and conference papers are listed.

1. JETCAS: S. A. Khan, M. Oli-Uz-Zaman, and J. Wang, "PAWN: Programmed Analog Weights for Non-linearity Optimization in Memristor-based Neuromorphic Computing System," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 1, pp. 436–444, March 2023. [pdf]

2. JETCAS: M. Oli-Uz-Zaman, S. A. Khan, W. Oswald, Z. Liao, and J. Wang, "Stuck-At-Fault Immunity Enhancement of Memristor-Based Edge AI Systems," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 4, pp. 922–933, December 2022. [pdf]

3. TED: J. Fu, Z. Liao, and J. Wang, "Level Scaling and Pulse Regulating to Mitigate the Impact of the Cycle-to-Cycle Variation in Memristor-Based Edge AI System," IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1752-1762, April 2022. [pdf]

4. JLPEA: M. Oli-Uz-Zaman, S. A. Khan, G. Yuan, Z. Liao, J. Fu, C. Ding, Y. Wang, and J. Wang, "Mapping Transformation Enabled High Performance and Low Energy Memristor-Based DNNs," Journal of Low Power Electronics and Applications, vol. 12, no. 1, pp. 10:1-14, March 2022. [pdf] Peer Reviewed Invited Paper and only Feature Paper in the entire issue (18 papers in total). 

5. TC: Z. Liao, J. Fu, and J. Wang, "Ameliorate Performance of Memristor Based ANNs in Edge Computing," IEEE Transactions on Computers, vol. 70, no. 8, pp. 1299-1310, August 2021. [pdf] 

6. IOTJ: J. Fu, Z. Liao, J. Liu, S. C. Smith, and J. Wang, “Memristor Based Variation Enabled Differentially Private Learning Systems for Edge Computing in IoT,” IEEE Internet of Things Journal (Impact Factor 9.936), vol. 8, no. 12, pp. 9672-9682, June 2021. [pdf]

7. TVLSI: J. Fu, Z. Liao, and J. Wang, “Memristor-Based Neuromorphic Hardware Improvement for Privacy-Preserving ANN,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 12, pp. 2745-2754, December 2019. [pdf]

8. JETCAS: J. Fu, Z. Liao, N. Gong, and J. Wang, “Mitigating Nonlinear Effect of Memristive Synaptic Device for Neuromorphic Computing,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 2, pp. 377-387, June 2019. [pdf]

9. ACCESS: J. Edstrom, Y. Gong, A. A. Haidous, B. Humphrey, M. E. McCourt, Y. Xu, J. Wang, and N. Gong, “Content-Adaptive Memory for Viewer-Aware Energy-Quality Scalable Mobile Video Systems,” IEEE Access, vol. 7, pp. 47479-47493, April 2019. [pdf]

10. TBD: J. Edstrom, D. Chen, Y. Gong, J. Wang, and N. Gong, “Data-Pattern Enabled Self-Recovery Low-Power Storage System for Big Video Data,” IEEE Transactions on Big Data, vol. 5, no. 1, pp. 95-105, January-March 2019. [pdf] 

11. TVLSI: X. Chen, S. A. Pourbakhsh, J. Fu, N. Gong, and J. Wang, “A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 7, pp. 1277-1289, July 2018. [pdf]

12. TVLSI: D. Chen, J. Edstrom, Y. Gong, P. Gao, L. Yang, M. McCourt, J. Wang, and N. Gong, “Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 4, pp. 684-696, April 2018. [pdf]

13. MEE: L. Hou, T. Ye, Q. Luo, J. Fu, and J. Wang. “A Method to Alleviate Hot Spot Problem in 3D IC,” Elsevier's Microelectronic Engineering, vol. 190, no. 4, pp. 19-27, April 2018. [pdf]

14. JAS: L. Hou, F. Fan, J. Fu, and J. Wang, “Time-Varying Algorithm for Swarm Robotics,” IEEE/CAA Journal of Automatica Sinica, vol. 5, no. 1, pp. 217-222, January 2018. [pdf]

15. TCASII: J. Edstrom, Y. Gong, D. Chen, J. Wang, and N. Gong, “Data-Driven Intelligent Efficient Synaptic Storage for Deep Learning,” IEEE Transactions on Circuits and Systems II, vol. 64, no. 12, pp. 1412-1416, December 2017. [pdf]

16. TVLSI: N. Gong, S. A. Pourbakhsh, X. Chen, X. Wang, D. Chen, and J. Wang, “SPIDER: Sizing-Priority Based Application-Driven Memory for Mobile Video Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2625-2634, September 2017. [pdf]

17. TC: J. Wang, L. Wang, H. Yin, Z. Wei, Z. Yang, and N. Gong, “cNV SRAM: CMOS Technology Compatible Non-volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System,” IEEE Transactions on Computers, vol. 65, no. 4, pp. 1055-1067, April 2016. [pdf]

18. MEE: L. Hou, J. Fu, J. Wang, and N. Gong, “A Novel Thermal-aware Structure of TSV Cluster in 3D IC,” Elsevier's Microelectronic Engineering, vol. 153, no. 3, pp. 110-116, March 2016. [pdf]

19. TVLSI: J. Wang, N. Gong, and Eby G. Friedman, “PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low Power Microprocessors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 613-624, Feb. 2016. [pdf]

20. TVLSI: N. Gong, J. Wang, S. Jiang, R. Sridhar, “TM-RF: Aging Aware Power Efficient Register file Design for Modern Microprocessors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 7, pp. 1196-1209, July 2015. [pdf]

21. TCASI: N. Gong, J. Wang, R. Sridhar, “Variation Aware Sleep Vector Selection in Dual Vt Dynamic OR Circuits for Low Leakage Register File Design,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 7, pp. 1970-1983, July 2014. [pdf]

22. MER: N. Gong, S. Jiang, J. Wang, B. Aravamudhan, K. Sekar, and R. Sridhar, “Hybrid-Cell Register Files Design for Improving NBTI Reliability,” Elsevier’s Microelectronics Reliability, vol. 52, no. 9, pp. 1865-1869, September-October 2012. [pdf]

23. EL: N. Gong, J. Wang, S. Jiang, and R. Sridhar, “Clock-Biased Local Bit Line for High Performance Register Files,” IET’s Electronics Letters, vol. 48, no. 18, pp. 1104-1105, August 2012. [pdf]

24. JSSC: X. Peng, W. Sansen, L. Hou, J. Wang, and W. Wu, “Impedance Adapting Compensation for Low-Power Multistage Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 46, no. 2, pp. 445-451, February 2011. [pdf]

25. MEJ: J. Wang, I. Savidis, and E. G. Friedman, “Thermal Analysis of Oxide-confined VCSEL Arrays,” Elsevier’s Microelectronics Journal, vol. 42, no. 5, pp. 820-825, May 2011. [pdf]

26. MEE: J. Wang, N. Gong, L. Hou, X. Peng, S. Geng, and W. Wu, “Low Power and High Performance Dynamic CMOS XOR/XNOR Gate Design,” Elsevier’s Microelectronic Engineering, vol. 88, no. 8, pp. 2781-2784, August 2011. [pdf]

27. MER: J. Wang, N. Gong, L. Hou, X. Peng, R. Sridhar, and W. Wu, “Leakage Current, Active power, and Delay Analysis of Dynamic Dual Vt CMOS Circuits under P-V-T Fluctuations,” Elsevier’s Microelectronics Reliability, vol. 51, no. 9, pp. 1498-1502, September 2011. [pdf]

28. MEJ: N. Gong, B. Guo, J. Lou, and J. Wang, “Analysis and Optimization of Leakage Current Characteristics in Sub-65nm Dual Vt Footed Domino Circuits,” Elsevier’s Microelectronics Journal, vol. 39, no. 9, pp. 1149-1155, September 2008. [pdf]

1.  J. Fu, Z. Liao, and J. Wang, “Cycle-to-Cycle Variation Suppression in ReRAM-Based AI Accelerators,” IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE'23), Huntsville, AL, USA, 2023. 

2. J. Wang, F. Zhao, M. R. Khan, M.H. Tanim, and Z. Templin, "Three-dimensional Environmentally Sustainable Neuromorphic Computing System Based on Natural Organic Memristor," IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS'23), Phoenix, AZ, USA, 2023, pp. 182-186. NSF-CISE MWSCAS Participation Award (Student)

3. M. Oli-Uz-Zaman, S. A. Khan, W. Oswald, Z. Liao, and J. Wang, "Reconfigurable Mapping Algorithm based Stuck-At-Fault Mitigation in Neuromorphic Computing Systems," ACM Great Lakes Symposium on VLSI 2023 (GLSVLSI'23), Knoxville, TN, USA, 2023, pp. 261-266. 

4. M. Oli-Uz-Zaman, S. A. Khan, G. Yuan, Z. Liao , J. Fu, C. Ding, Y. Wang, and J. Wang, "Reliability Improvement in RRAM-based DNN for Edge Computing," IEEE International Symposium on Circuits and Systems (ISCAS'22), Austin, TX, USA, 2022, pp. 581-585.

5. Z. Liao, J. Fu, C. Ding, and J. Wang, “Pulse Truncation Enabled High Performance and Low Energy Memristor-based Accelerator”, IEEE SoutheastCon 2022, Mobile, AL, USA, 2022, pp. 473-478.

6. G. Yuan, Z. Liao, X. Ma, Y. Cai, Z. Kong, X. Shen, J. Fu, Z. Li, C. Zhang, H. Peng, N. Liu, A. Ren, J. Wang, Y. Wang, "Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI," 22nd IEEE International Symposium on Quality Electronic Design (ISQED'21), 2021, pp. 135-141.

7. G. Yuan, P. Behnam, Y. Cai, A. Shafiee, J. Fu, Z. Liao, Z. Li, X. Ma, J. Deng, J. Wang, M. Bojnordi, Y. Wang, and C. Ding, “TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators,” 2021 Design, Automation and Test in Europe Conference (DATE’21), 2021, pp. 926-931. Best Paper Nomination

8. J. Fu, Z. Liao, and J. Wang, “Cycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANN,” 33rd IEEE International SoC Conference (SoCC’20), 2020, pp. 66-71.

9. J. Fu, Z. Liao, N. Gong, and J. Wang, “Linear Optimization for Memristive Device in Neuromorphic Hardware,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI’19), 2019, Miami, FL, USA, pp. 453-458. Best Paper Nomination

10. J. Edstrom, D. Chen, Y. Gong, J. Wang, and N. Gong, “Bringing Offline Mining to Online Learning System: Low-Cost and Efficient Self-Healing Synaptic Storage for Deep Learning,” IEEE International Symposium on Circuits and Systems (ISCAS'17), 2017, Baltimore, MD, USA, Late Breaking News.

11. R. Ge, Z. Lin, N. Gong, and J. Wang, “Design and Performance Analysis of Energy Harvesting Sensor Networks with Supercapacitor,” IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS'17), 2017, Boston, MA, USA, pp. 64-67.

12. X. Chen, S. Pourbakhsh, N. Gong, and J. Wang, “Closed Form Delay Models for Buffer-driven TSVs in 3D On-chip Memory,” IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS'17), 2017, Boston, MA, USA, pp. 365-368.

13. J. Fu, S. Pourbakhsh, X. Chen, M. Li, Z. Lin, L. Hou, F. Haring, N. Gong, and J. Wang, “On-Chip Thermal Management Method Based on Phase Change Material,” IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS'17), 2017, Boston, MA, USA, pp. 985-988.

14. N. Gong, J. Edstrom, D. Chen, and J. Wang, “Data-Pattern Enabled Self-Recovey Multimedia Storage System for Near-Threshold Computation,” IEEE International Conference on Computer Design (ICCD'16), 2016, Phoenix, AZ, USA.

15. D. Chen, J. Edstrom, X. Chen, W. Jin, J. Wang, and N. Gong, “Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'16), 2016, San Francisco, CA, USA. Best Paper Nomination 

16. X. Chen, S. Pourbakhsh, L. Hou, N. Gong, and J. Wang, “Dummy TSV Based Bit-line Optimization in 3D On-chip Memory,” IEEE 2016 International Electro-Information Technology Conference (EIT'16), 2016, Grand Forks, ND, USA, pp. 580-585. Best Paper Award 

17. S. A. Pourbakhsh, X. Chen, D. Chen, X. Wang, N. Gong, J. Wang, “Sizing-Priority Based Low-Power Embedded Memory for Mobile Video Applications,” IEEE International Symposium on Quality Electronic Design (ISQED’16), 2016, Santa Clara, USA, pp. 1-5. Best Paper Nomination

18. J. Edstrom, D. Chen, J. Wang, M. McCourt, and N. Gong, “Luminance Adaptive Smart Video Storage System,” IEEE International Symposium on Circuits and Systems (ISCAS’16), 2016, Montreal, Canada, pp. 734-737.

19. D. Chen, X. Wang, J. Wang, and N. Gong, “VCAS: Viewing Context Aware Power-Efficient Mobile Video Embedded Memory,” IEEE International SoC Conference (SoCC’15), 2015, Beijing, China, pp. 333-338.

20. N. Gong, J. Wang, and R. Sridhar, “Application-Driven Power Efficient ALU Design Methodology for Modern Microprocessors,” International Symposium on Quality Electronic Design (ISQED’13), 2013, Santa Clara, CA, pp. 184-188.

21. N. Gong, G. Tang, J. Wang, and R. Sridhar “Novel Adaptive keeper LBL technique for Low Power and High Performance Register files,” 24th IEEE International SoC Conference (SoCC’11), 2011, Taipei, Taiwan, pp. 30-35.

22. N. Gong, G. Tang, J. Wang, and R. Sridhar, “Low Power Tri-State Register Files Design for modern out-of-order processors,” 24th IEEE International SoC Conference (SoCC’11), 2011, Taipei, Taiwan, pp. 323-328.

23. N. Gong, J. Wang, and R. Sridhar, “PVT Variations Aware Optimal Sleep Vector Determination of Dual Vt Domino OR Circuits,” 24th IEEE International SoC Conference (SoCC’11), 2011, Taipei, Taiwan, pp. 359-364.

24. J. Wang, N. Gong, W. Wu, and L. Hou, “Fan-in Sensitive Low Power Dynamic Circuits Performance Statistical Characterization,” 23rd IEEE International SoC Conference (SOCC’10), 2010, Las Vegas, USA, pp. 321-325. 

25. J. Wang, W. Wu, N. Gong, and L. Hou, “Domino Gate with Modified Voltage Keeper,” 11th International Symposium on Quality Electronic Design (ISQED’10), 2010, Santa Clara, USA, pp. 443-446. 

26. J. Wang, W. Wu, N. Gong, L. Zuo, X. Peng, and L. Hou, “Wavelet Neural Networks Based Performance Estimation for Power Gating Domino Circuits,” 2009 IEEE International Conference on Information and Automation (ICIA’09), 2009, Zhuhai, China, pp. 435-438. 

27. J. Wang, N. Gong, W. Wu, L. Hou, S. Geng, W. Zhang, and X. Peng, “Using Charge Self-compensation Domino Full-adder with Multiple Supply and Dual Threshold Voltage in 45nm,” 10th International Conference on ULtimate Integration of Silicon (ULIS’09), 2009, Aachen, Germany, pp. 225-228. 

28. J. Wang, N. Gong, W. Wu, L. Zuo, L. Hou, X. Peng, and D. Gao, “Power and Delay Estimation for Dynamic OR Gates with Header and Footer Transistor Based on Wavelet Neural Networks,” 10th International Conference on ULtimate Integration of Silicon (ULIS’09), 2009, Aachen, Germany, pp.  241-244. 

29. J. Wang, L. Zuo, N. Gong, D. Gao, S. Geng, W. Zhang, L. Hou, X. Peng, and W. Wu, “Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks,” 2009 International Symposium on Neural Networks (ISNN’09), 2009, Wuhan, China, pp. 844-851. 

30. L. Zuo, J. Wang, L. Hou, S. Geng, and W. Wu, “Fault Diagnosis of Analog IC based on Wavelet Neural Network Ensemble,” 2009 International Symposium on Neural Networks (ISNN’09), 2009, Wuhan, China, pp. 772-779. 

31. J. Wang, W. Wu, N. Gong, L. Zuo, L. Hou, S. Geng, W. Zhang, and D. Gao, “Switching and Leakage Power Modeling for Multiple-supply Dynamic Gate with Delay Constraining Based on Wavelet Neural Networks,” 2009 International Joint Conference on Neural Networks (IJCNN’09), 2009, Atlanta, GA, USA, pp. 3240-3243.