Intelligent Multi-Level Power-Aware Circuits and sysTems (IMPACT) Lab 

Memristors for Neuromorphic Design

A memristor chip is designed and fabricated for neuromorphic microprocessor. A memristor is an analog device to exploit the multilevel conductance states and to regulate the flow of electrical current. Typically, memristors are connected as a crossbar structure, where memristors are positioned in each cross point acting as synapses in a neural network. [Related Paper JETCAS'19 TVLSI'19 IOTJ'21 TC'21 JLPEA'22 TED'22 JETCAS'22 JETCAS'23]

3D Integrated Circuits

A 3-D test circuit comprised five silicon layers has been fabricated to experimentally analyze power distribution, horizontal and vertical thermal coupling, and cross-layer microprocessor. Each device layer is manufactured in 130-nm Chartered CMOS technology before 3D bonding, TSV fabrication, and wafer thinning by Tezzaron. [Related Paper MEE'16 MEE'18 TVLSI'18]

Video Embedded SRAM 

A test chip is fabricated to develop an sizing-priority based application-driven memory for low-power mobile video applications. We investigated the size dependent memory failure characteristics and modeled the influence of the memory failure on video output, connecting the hardware design and application requirement. [Related Paper TVLSI'17]

Ultra-low Power Non-volatile SRAM 

A CMOS compatible non-volatile SRAM (cNV SRAM) is fabricated to achieve energy efficient on-chip memory. It works as conventional 8T SRAM to keep high speed in work mode; in sleep mode, it backs up the data in NV component and switches off the power supply, thereby minimizing the leakage energy without data loss. [Related Paper TC'16] 

Microprocessor Based on PNS-FCR 

A test chip is fabricated to verify a p-type/n-type dynamic circuit selection (PNS) algorithm and a flexible charge recycling (FCR) design methodology for data path design. The measurement results demonstrate that the proposed ALU reduces power consumption by 31%, validating the ability of PNS-FCR to save power. [Related Paper TVLSI'16] 

Multistage Impedance Adapting Compensation (IAC) amplifier 

A three-stage IAC amplifier is implemented and fabricated in a 0.35 um CMOS technology. The IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product of 4.4 MHz while dissipating only 30 uW power with a 1.5 V supply. [Related Paper JSSC'11] 

Other Chips

Many chips are also fabricated to respectively verify digital, analog, and emerging memory design, such as power efficient microprocessors, programmable amplifier, and tri-state based register files.