Research

Research Interests

• Single photon emitters in Transition Metal Dichalcogenides

• Oriented growth of single crystalline tellurium without epitaxy

• Elemental tellurium as a semiconductor material for back end of the line integration with CMOS electronics

• Gated photoluminescence in quantum dot thin films

• Low voltage AC electroluminescence in silicon MOS capacitors

• Analytical modeling of nanoscale device using self-consistent approach 

Supervisor

Ali Javey, Professor, Electrical Engineering and Computer Sciences, UC Berkeley [Website]

Research Experience

1. Aligning crystal orientation of Tellurium using nanoscale templates

Here we explore the control over the intrinsic anisotropy of tellurium to reduce device variability. As a result, we are able to probe the intrinsic one-dimensional physics of elemental tellurium which remain inaccessible in the bulk limit.

2. Performance limits of tellurium based semiconductors

We studied the thermal stability of contacts to tellurium for back end of the line integration to CMOS technology. We identified ruthenium as a promising material for electrode which shows very little inter-diffusion at elevated temperatures.

3. Gated Photoluminescence in Quantum Dot Thin Films

In this work, we optimized a device structure for gating thin film quantum dots and analyzing the various recombination pathways under charge injection. This sheds light into the degradation mechanism of bright core-shell nanocrystals (quantum dots) which loose efficiency over prolonged operation as a result of charging.

4. Electroluminescence in Silicon MOS Capacitors

We fabricated MOS transistors in CMOS framework. Optical and electrical characterization were performed to investigate the origin of electroluminescence in indirect bandgap silicon with AC pulses. Theoretical model supports hot carrier injection during the sharp transition of the pulses, which recombine both radiatively and non-radiatively. The radiative path of the recombination yields the observed electroluminescence.

5. Drain current modeling of InGaAs gate-all-around MOSFET

The gate-all-around transistor is the most resilient device of the multi-gate architecture in terms of immunity from short channel effects (SCEs). InGaAs planar MOSFET and double channel FETs have paved the path for replacing Si CMOS technology with the immense boost in on-state as well as off-state performance. The need for compact models is evident for industrial fabrication of InGaAs-based transistors. This work elaborates on the evolution of an analytic drain current model that circumvents regional approach, which is valid from depletion to strong inversion. In order to cohere with the physics involved in a real device, several non-ideal effects have been incorporated. The inclusion of interface trap defects is imperative for high-k dielectrics where integration of a suitable gate dielectric has thwarted the efforts of its fabrication for over four decades. A rigorous analysis of the impact of variation of physical parameters and process metrics on device performance are studied in this work.  Relevant Publication: AIP Advances 2021

6. Electrostatic characterization of inversion type InGaAs gate-all-around MOSFET

In spite of intense research in the exploration of high mobility channel InGaAs as a suitable candidate for the next generation planar MOSFET to replace Silicon, the immediacy of an analytical approach that better captures the electrostatics of the novel III-V channel is evident over existing silicon based compact models. This calls for an efficient electrostatic model that incorporates interface trap defects between the Al2O3-semiconductor interface as well as reflect volume inversion in ultra scaled dimensions as portrayed in numerical simulation in the literature. This work addresses the analytical formalism of an InGaAs nanowire MOSFET for electrostatic CV characterization and proposes a threshold voltage model to study the impact of dimension scaling and material properties. Relevant Publication: J. Comp. 2021

7. Surface potential based modeling of electrostatics and transport phenomena in GaN based nanowire junctionless MOSFET

Apart from electrostatics, the transport characterization of the GaN junctionless device is essential in order to fully comprehend the underlying physics of the GaN nanowire MOSFET, before implementing in circuit models. The analytical drain current model is developed for a short channel nanowire MOSFET, complemented with certain non-ideal effects, to emulate the properties of a real device. Excellent match between model and reported experimental demonstrations adduces the validity of the proposed model in the sub-nanometer gate length. Relevant Publications: TED 2020

8. Capacitance-voltage characteristics of GaN nanowire junctionless MOSFET

Research on GaN nanowire is still premature and underlies prospects in switching application besides power devices, thanks to the wide bandgap of the GaN and the high electron mobility in the channel material. While certain long channel nanowires have been experimentally demonstrated in the literature, a robust analytical model is still lacking, underscoring the need to develop a physics based model for circuit simulation. An analytical approach to evaluate the electrostatic properties of the junctionless MOSFET is explored in this work, first in different modes of operation and later unified by a smoothing approximation. The electrostatic potential is essential in understanding the transition of the modes of operation, while the impact on several process parameters helps us to predict the performance variability of the GaN device under operation. Relevant Publications: IEEE Nano 2020

9. Analytical modeling of electrostatics and transport properties of enhancement mode double channel HEMT

The High Electron Mobility Transistor (HEMT) is a novel class of device suitable for high frequency power needs. Recently, double channel operation of HEMT has been demonstrated using GaN having high mobility channel. From the superior current drive, it becomes imperative to study the device physics. The proposed model provides a clear conception of the GaN HEMT physics, providing an in-depth analysis of the inter-channel coupling at the onset of first/lower channel with the second/upper channel. The carrier concentration change with gate bias reveals the underlying mechanism of inter-channel coupling in the double channel transistor. This fact is further corroborated from the variation of capacitance-voltage profile at the onset of channel formation. The threshold voltage obtained interactively from the CV profile exhibits enhancement mode operation of the MOS-HEMT. Relevant Publications: TED 2019, NMDC 2018  

10. Quantum  Mechanical Simulation of double channel GaN MOS-HEMT

The High Electron Mobility Transistor (HEMT) is a high frequency power device. The employment of GaN as channel material enhances the mobility as well as device performance in sub-micron length. Experimental demonstration of double channel HEMT with superior performance calls for its modeling for future implementation of these devices in power application. The self-consistent Schrodinger-Poisson simulation is a robust means of exploring the electrostatics for these power transistors. The self-consistent simulation reveals the double channel operation through quantum mechanical effects and traces the transition of capacitance-voltage profile at the onset of either channels. Relevant Publication: NMDC 2018