Publications

Journals & Conferences

• Jaeho Lee, Kyongsu Lee, Jae-Yoon Sim, and Seon-Kyoo Lee, “A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect”, IEEE Symposium on VLSI Technology and Circuits (VLSI), 2024.(ACCEPTED) 

• Dongjun Park, Heesung Roh, Seon-Kyoo Lee, and Jae-Yoon Sim , “A 94fsrms-Jitter and −249.3dB FoM 4.0GHz Ring-Oscillator-based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch”, IEEE Symposium on VLSI Technology and Circuits (VLSI), 2024.(ACCEPTED) 

• Na D., Lee J.-W., Lee S.-K., Cho H., Lee J., Yang M., Song E., Kavala A., Kim T., Jang D.-S., Jo Y., Shin J.-Y., Chun B.-K., Lee T.-S., Jeong B., Yoon C.-W., Kang D., Lee S., Ihm J., Byeon D.S., Lee J., Song J.H., “A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package with F-Chip for High-Performance and High-Capacity Storage”, IEEE Journal of Solid-State Circuits(JSSC), vol. 56, no. 4, pp.1129-1140, Apr. 2021.

• Chi-Weon Yoon, Hyung-Gon Kim, Seon-Kyoo Lee, Jinyub Lee, Jai Hyuk Song, “Issues and Key Technologies for Next Generation 3D NAND”, IEEE Int. Conf. on Electronics, Information, and Communication, Feb. 2021. 

• Lee J.-W., Na D., Kavala A., Cho H., Lee J., Yang M., Song E., Kim T., Lee S.-K., Jang D.-S., Chun B.-K., Jo Y., Jung S., Jung D.-I., Kim C., Kang D., Lee T.-S., Jeong B., Yoon C., Kang D., Lee S., Ihm J., Byeon D.S., Lee J.-Y., Hwang S., Song J.H., “A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems”, IEEE Symp. on VLSI Circuits, Jun. 2020. 

• S Lee, J-Y Lee, I-H Park, J Park, S-W Yun, M-S Kim, J-H Lee, M Kim, K Lee, T Kim, B Cho, D Cho, S Yun, J-N Im, H Yim, K-H Kang, S Jeon, S Jo, Y-L Ahn, S-M Joe, S Kim, D-K Woo, J Park, H-W Park, Y Kim, J Park, Y Choi, M Hirano, J-D Ihm, B Jeong, S-K Lee, M Kim, H Lee, S Seo, H Jeon, C-H Kim, H Kim, J Kim, Y Yim, H Kim, D-S Byeon, H-J Yang, K-T Park, K-H Kyung, J-H Choi, “128Gb 2b/cell NAND flash memory in 14nm technology with tPROG= 640µs and 800MB/s I/O rate”, IEEE Int. Solid-State Circuits Conf. (ISSCC), vol. 59, Feb. 2016. 

• H-J. Kim, J-D. Lim, J-W. Lee, D-H. Na, J-H. Shin, C-H. Kim, S-W. Yu, J-Y. Shin, S-K. Lee, D. Rajagopal, S-T. Kim, K-T. Kang, J-J. Park, Y-J. Kwon, M-J. Lee, S-H. Kim, S-H. Shin, H-G. Kim, J-T. Kim, K-S. Kim, H-S. Joo, C-J. Park, J-H. Kim, M-J. Lee, D-K. Kim, H-J. Yang, D-S. Byeon, K-T. Park, K-H. Kyung, J-H. Choi, “1GB/s 2Tb NAND Flash Multi-Chip Package with Frequency-Boosting Interface Chip”, IEEE Int. Solid-State Circuits Conf. (ISSCC), vol. 58, Feb. 2015. 

• Hyunsoo Ha, Seon-Kyoo Lee, Byumgsub Kim, Hong-June Park, and Jae-Yoon Sim, “A 0.5-V, 1.47-μW, 40-kS/s, 13-bit SAR ADC With Capacitor Error Compensation”, IEEE Trans. On Circuits and Systems II (TCAS-II), vol.61, no.11, pp.840-844, Nov. 2014. 

• Seung-Hun Lee, Seon-Kyoo Lee, Byumgsub Kim, Hong-June Park, and Jae-Yoon Sim, “Current-Mode Transceiver for Silicon Interposer Channel”, IEEE Journal of Solid-State Circuits (JSSC), vol.49, no.9, pp.2044-2053, Sep. 2014. 

• Seon-Kyoo Lee, Byumgsub Kim, Hong-June Park, and Jae-Yoon Sim, “A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation”, IEEE Journal of Solid-State Circuits (JSSC), vol.48, no.9, pp.2118-2127, Sep. 2013. 

• Seon-Kyoo Lee, Seung-Hun Lee, Dennis Sylvester, David Blaauw, Jae-Yoon Sim, “A 95 fJ/b Current-Mode Transceiver for 10mm On-Chip Interconnect”, IEEE Int. Solid-State Circuits Conf. (ISSCC), vol. 56,  pp. 262-263, Feb. 2013.  

• Seon-Kyoo Lee, Byumgsub Kim, Hong-June Park, and Jae-Yoon Sim, “A QDR-Based 6 GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte-CDR for Memory Interface”, IEEE Trans. On Circuits and Systems II (TCAS-II), vol. 60, no. 2, Feb. 2013. 

• Hyunsoo Ha, Yunjae Suh, Seon-Kyoo Lee, Hong-June Park, and Jae-Yoon Sim, “A 0.5V, 11.3-μW, 1-kS/s Resistive Sensor Interface Circuit with Correlated Double Sampling”, IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2012.  

• Seon-Kyoo Lee, Hyunsoo Ha, Hong-June Park, Jae-Yoon Sim, “A 5 Gb/s Single-Ended Parallel Receiver With Adaptive FEXT Cancellation”, IEEE Int. Solid-State Circuits Conf. (ISSCC), vol. 55,  pp.140-141, Feb. 2012.   

• Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo Sun Choi, Hong-June Park, Jae-Yoon Sim, “An 8GB/s Quad-Skew Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface”, IEEE Int. Solid-State Circuits Conf. (ISSCC), vol. 55, pp.136-137, Feb. 2012.    

• Seon-Kyoo Lee, Young-Sang Kim, Hong-June Park, Jae-Yoon Sim “A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition”, Journal of Electrical and Computer Engineering, vol.2011, Article ID 701730, June. 2011. 

• Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, and Jae-Yoon Sim “A 21fJ/Conversion-Step 100KS/s 10-bit ADC with a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface”, IEEE Journal of Solid-State Circuits (JSSC), vol.46, no.3, pp.651-659, Mar. 2011. 

• Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim, “A 110 MHz-to-1.4 GHz Locking 40-Phase All-Digital DLL” IEEE Journal of Solid-State Circuits (JSSC), vol.46, no.2, pp.435-444, Feb. 2011. 

• Young-Hun Seo, Seon-Kyoo Lee, and Jae-Yoon Sim, “A 1GHz Digital PLL with a 3ps-Resolution Floating-Point Number TDC in a 0.18 μm CMOS”, IEEE Trans. on Circuits and Systems II (TCAS-II), vol.58, no.2, pp.70-74, Feb. 2011. 

• Seon-Kyoo Lee, Young-Hun Seo, Hong-June Park, Jae-Yoon Sim, “1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μm CMOS” , IEEE Journal of Solid-State Circuits (JSSC), vol.45, no.12, pp.2874-2881, Dec. 2010. 

• Seung-Jin Park, Jun Choi, Gan Young Park, Seon-Kyoo Lee, Youngsu Cho, Ji In Yun, Sangmin Jeon, Kyong Tai Kim, Jae Koo Lee, Jae-Yoon Sim, “Inactivation of S. mutans Using an Atmospheric Plasma Driven by a Palm-Size-Integrated Microwave Power Module”, IEEE Trans. on Plasma Science, vol.38, no.8, pp.1956-1962, Aug. 2010. 

• Jae-Yoon Sim, Seon-Kyoo Lee, Young-Sik Kim, Young-Soo Sohn, and Joo Sun Choi, “High-Speed Links for Memory Interface”, IEEE Int. Conf. on IC Design and Tech.(ICICDT), pp.16-19, Jun. 2010.

• Seon-Kyoo Lee, Young-Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim, “A 1GHz ADPLL with a 1.25ps Minimum-Resolution Sub-Exponent TDC in 0.18μm CMOS”, IEEE Int. Solid-State Circuits Conf. (ISSCC),  vol. 53, pp.482-483, Feb. 2010. 

• Seon-Kyoo Lee, Seung-Jin Park, Yunjae Suh, Hong-June Park, Jae-Yoon Sim, “ A 1.3μW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18μm CMOS”, IEEE Symp. on VLSI Circuits, pp.242-243, Jun. 2009. 

• Seon-Kyoo Lee, Young-Sang Kim, Hyunsoo Ha, Younghun Seo, Hong-June Park, Jae-Yoon Sim, “A 650Mb/s-to-8Gb/s Referenceless CDR Circuit with Automatic Acquisition of Data Rate” IEEE Int. Solid-State Circuits Conf. (ISSCC), vol. 52, pp.184-185, Feb. 2009. 

• Seon-Kyoo Lee, Dong-Woo Jee, Yunjae Suh, Hong-June Park, and Jae-Yoon Sim, “A 8 GByte/s Transceiver with Current-Balanced Pseudo-Differential Signaling for Memory Interface”, IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp.237-240, Nov. 2008. 

• Seon-Kyoo Lee, Kyungho Lee, Hong-June Park, and Jae-Yoon Sim, “FEXT-eliminated stub-alternated microstrip line for multi-Gb/s parallel links”, IET Electronics Letters, vol.44, no.4, Feb. 2008. 

• Seon-Kyoo Lee, Young-Sang Kim, Hong-June Park, and Jae-Yoon Sim, “A SSN-Reduced 5 Gb/s Parallel Transmitter”, IEEK J. Semicond. Tech. and Sci., vol.7, no4, pp.235-240, Dec. 2007. 

• Seon-Kyoo Lee, Young-Sang Kim, Hong-June Park, and Jae-Yoon Sim, “A 5 Gb/s 16-bit Transmitter with Segmented Group-Inversion Encoding”, IEEK Int. SoC Design Conf., pp.223-226, Oct. 2007. 

Patents

• Memory device including multiple memory chips and data signal lines and a method of operating the memory device, US11810638, 2023.11.07

• NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE, US18217063, 2023.10.26

• Memory device supporting DBI interface and operating method of memory device, US11756592, 2023.09.12

• Nonvolatile memory device supporting high-efficiency I/O interface, US11714579, 2023.08.01

• STORAGE DEVICE AND RETRAINING METHOD THEREOF, US18077406, 2023.04.06

• SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT, US17994296, 2023.03.23

• Semiconductor device including delay compensation circuit, US 11522550, 2022.12.06

• Multi-chip package with reduced calibration time and ZQ calibration method thereof, US11475955, 2022.10.18

• Nonvolatile memory device supporting high-efficiency I/O interface, US11372593, 2022.06.28

• Storage device and retraining method thereof, US11550498, 2023.01.10

• Multi-mode transmission line and storage device including the same, US11522261, 2022.12.06

• Multi-chip package with reduced calibration time and ZQ calibration method thereof, US11217283, 2022.01.04

• Multi-chip package with reduced calibration time and ZQ calibration method thereof, US11127462, 2021.09.21

• Semiconductor package, US10666249, 2020.05.26

• Method and circuit for self-training of a reference voltage and memory system including the same, US10497412, 2019.12.03

• Apparatus and method of transmitting and receiving data, and semiconductor package including the same, US10438635, 2019.10.08

• Reference voltage generator and semiconductor device including the same, US10439632, 2019.10.08

• Reception interface circuits supporting multiple communication standards and memory systems including the same, US10291275, 2019.05.14

• Equalizer circuit and integrated circuit including the same, US10171269, 2019.01.01

• Semiconductor chip, test system, and method of testing the semiconductor chip, US10132865, 2018.11.20

• Method and circuit for self-training of a reference voltage and memory system including the same, US10014039, 2018.07.03

• Solid state driving including nonvolatile memory, random access memory and memory controller, US09886379, 2018.02.06

• Semiconductor memory system, semiconductor memory device and method of operating the semiconductor memory device, US09767873 2017.09.19

• Storage device including nonvolatile memory and memory controller and operating method of retiming circuit interfacing communication between nonvolatile memory and memory controller, US09601171, 2017.03.21