M.S. & Ph. D. in EE POSTECH, 2012
B.S. in EE Hanyang Univ., 2006
2023. 9 - Present : Assistant professor, Dept. of Semiconductor Engineering, POSTECH
2024. 5 - Present : Director of Research Center for Memory Semiconductor (IC2MS), POSTECH
2019. 3 - 2023. 8 : Principal Engineer, Memory Division, Samsung Electronics
2012. 9 - 2019. 2 : Staff Engineer, Memory Division, Samsung Electronics
2011. 8 - 2012. 7 : Visiting Researcher, Univ. of Michigan, Ann arbor, US
Excellent patent award, Samsung electronics, 2020
Excellent thesis award, EE POSTECH, 2012
Bronze prize, Samsung human tech thesis competition, 2012
Bronze prize, Samsung human tech thesis competition, 2010
Silver prize, Samsung human tech thesis competition, 2009
High-speed / Low-power Interface Circuits Design: Equalizing circuits, Clock generation circuits, CDR circuits
On-chip Interconnect Circuits Design : Die-to-die interface, Silicon interposer transceiver circuits
Memory Interface Circuits Design : DDR interace, Crosstalk cancellation
Analog & Mixed-mode Circuits Design : Data converters