Integrated Circuits for Energy Harvesting Applications

About ICEHA

Since 2012, integrated circuit (IC) designs for low-power applications have been the focus of major research by Prof. Fabián, who obtained the M.Sc. (2013) and D.Sc. (2017) degrees advised by Prof. Petraglia from the Federal University of Rio de Janeiro (UFRJ). Since 2018, Prof. Fabián has been a professor at CEFET/RJ, and a collaboration in research between the laboratories of CEFET/RJ and PADS/UFRJ (Prof. Petraglia) has been established by advising undergraduate, M.Sc., and D.Sc. degree students in cooperation and publishing the resulting research in well-known journals and international conferences. The Microelectronics Group (GME) of CEFET/RJ was created in 2018, developing different research projects in the design of analog and mixed-signal integrated circuits for ultra-low-power systems, especially focused on contributions for self-powered ICs in energy harvesting applications. The techniques and design methodologies that we have developed throughout our research contribute to the evolution of electronic devices and bring benefits to the environment by enabling the use of alternative energies for powering systems on chips.

Current Research

Computer-Aided Design Tools for Low-Power LDO Regulators


A Clonal Selection Algorithm Applied to Charge Pump Designs


Integrated Circuits for Wide-Temperature-Range Energy Harvesting


Student Publications

Conference: 17th Argentina School of Micro-Nanoelectronics, Technology and Applications, Córdoba, Argentina, March  6-10, 2023.

Title: Nano-Ampere Area-Efficient Current Reference Based on Temperature-Controlled Pseudo-Resistor


Conference: 28th IBERCHIP Workshop, Santiago, Chile, 2022.  

Title: Settling Time Modeling of the N-Stage Charge Pump Doubler Using Z Transform 


Conference: 2022 IEEE 13th Latin American Symposium on Circuits & Systems (LASCAS), Santiago, Chile. 

Title: Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node 


Journal:  IEEE Transactions on Circuits and Systems I: Regular Papers

Title: A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 


Conference: 2021 IEEE 12th Latin American Symposium on Circuits & Systems (LASCAS), Arequipa, Peru. 

Title: A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 


Conference: 27th IBERCHIP Workshop, Arequipa, Peru, 2021. 

Title: A Computer-Aided Approach for Low-Power LDO Regulator Design


Conference: Microelectronics Students Forum (SFORUM) 2019, São Paulo, Brazil

Title: Analysis of Intrinsic Noise for 3T CMOS Voltage References


Conference: Microelectronics Students Forum (SFORUM) 2019, São Paulo, Brazil

Title: Study of Low-Power Circuits for Thermoelectric Harvesting in 28 nm FD-SOI CMOS Technology

Journal Publications

Title: Ultra-low-power CMOS voltage references: Analysis and optimization regarding technology node


Title: A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 


Title: A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design


Title: Gate leakage compensation technique for self-cascode based voltage references


Title: Adjustable Output CMOS Voltage Reference Design


Title: Closed-Form Analysis of Metastability Voltage in 28 nm UTBB FD-SOI CMOS Technology


Title: Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology


Title: A Computer-Aided Approach for Voltage Reference Circuit Design

International Conference Presentations

Nano-Ampere Area-Efficient Current Reference Based on Temperature-Controlled Pseudo-Resistor


Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node


Settling Time Modeling of the N-Stage Charge Pump Doubler Using Z Transform


A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design (TCAS-II Invited paper)


A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 


A Computer-Aided Approach for Low-Power LDO Regulator Design


Adjustable Output CMOS Voltage Reference Design


Closed-Form Analysis of Metastability Voltage in 28 nm UTBB FD-SOI CMOS Technology


Analytic Modeling of Static Noise Margin Considering DIBL and Body Bias Effects


Analytic boundaries for 6T-SRAM design in standby mode


A Computer-Aided Approach for Voltage Reference Circuit Design