Since 2012, integrated circuit (IC) designs for low-power applications have been the focus of major research by Prof. Fabián, who obtained the M.Sc. (2013) and D.Sc. (2017) degrees advised by Prof. Petraglia from the Federal University of Rio de Janeiro (UFRJ). Since 2018, Prof. Fabián has been a professor at CEFET/RJ, and a collaboration in research between the laboratories of CEFET/RJ and PADS/UFRJ (Prof. Petraglia) has been established by advising undergraduate, M.Sc., and D.Sc. degree students in cooperation and publishing the resulting research in well-known journals and international conferences. The Microelectronics Group (GME) of CEFET/RJ was created in 2018, developing different research projects in the design of analog and mixed-signal integrated circuits for ultra-low-power systems, especially focused on contributions for self-powered ICs in energy harvesting applications. The techniques and design methodologies that we have developed throughout our research contribute to the evolution of electronic devices and bring benefits to the environment by enabling the use of alternative energies for powering systems on chips.

• Igor Meirelles Martins - MSc Candidate (CEFET/RJ)

Computer-Aided Design Tools for Low-Power LDO Regulators

• Ricardo da Silva Alves Junior - MSc Candidate (CEFET/RJ)

A Clonal Selection Algorithm Applied to Charge Pump Designs

• Italo Bruni Oliveira Rodrigues - Ph.D. Candidate (UFRJ)

Integrated Circuits for Wide-Temperature-Range Energy Harvesting

• Italo Bruni (UFRJ), Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Conference: 17th Argentina School of Micro-Nanoelectronics, Technology and Applications, Córdoba, Argentina, March  6-10, 2023.

Title: Nano-Ampere Area-Efficient Current Reference Based on Temperature-Controlled Pseudo-Resistor

• Humberto Matheus Costa Abádio (CEFET/RJ), Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Conference: 28th IBERCHIP Workshop, Santiago, Chile, 2022.  

Title: Settling Time Modeling of the N-Stage Charge Pump Doubler Using Z Transform 

• Lucas Souza da Silva (CEFET/RJ), Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Conference: 2022 IEEE 13th Latin American Symposium on Circuits & Systems (LASCAS), Santiago, Chile. 

Title: Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node 

• Carlos A. Pinheiro Jr. (CEFET/RJ), Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Journal:  IEEE Transactions on Circuits and Systems I: Regular Papers

Title: A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 

• Carlos A. Pinheiro Jr. (CEFET/RJ), Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Conference: 2021 IEEE 12th Latin American Symposium on Circuits & Systems (LASCAS), Arequipa, Peru. 

Title: A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 

• Igor Meirelles Martins  (CEFET/RJ), Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Conference: 27th IBERCHIP Workshop, Arequipa, Peru, 2021. 

Title: A Computer-Aided Approach for Low-Power LDO Regulator Design

• Marcella C G De Moraes (CEFET/RJ), Pedro Henrique Leite (UFRJ), Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Conference: Microelectronics Students Forum (SFORUM) 2019, São Paulo, Brazil

Title: Analysis of Intrinsic Noise for 3T CMOS Voltage References

• Carlos A. Pinheiro Jr. (CEFET/RJ), , Fabian Olivera (CEFET/RJ) and Antonio Petraglia (UFRJ).

Conference: Microelectronics Students Forum (SFORUM) 2019, São Paulo, Brazil

Title: Study of Low-Power Circuits for Thermoelectric Harvesting in 28 nm FD-SOI CMOS Technology

• AEU - International Journal of Electronics and Communications, Volume 164, March 2023:

Title: Ultra-low-power CMOS voltage references: Analysis and optimization regarding technology node

• IEEE Transactions on Circuits and Systems I: Regular Papers, September 2021:

Title: A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 

• IEEE Transactions on Circuits and Systems II: Express Briefs, December 2020: 

Title: A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design

• Electronics Letters, Volume 56, Issue 22, October 2020:

Title: Gate leakage compensation technique for self-cascode based voltage references

• IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 67, Issue 10, October 2020: 

Title: Adjustable Output CMOS Voltage Reference Design

• IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 67, Issue 4, April 2020:

Title: Closed-Form Analysis of Metastability Voltage in 28 nm UTBB FD-SOI CMOS Technology

• Microelectronics Journal, Volume 78, August 2018:

Title: Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology

• Analog Integrated Circuits and Signal Processing, Volume 89, Issue 3, March 2016:

Title: A Computer-Aided Approach for Voltage Reference Circuit Design

• 17th Argentina School of Micro-Nanoelectronics, Technology and Applications, Córdoba, Argentina, March  6-10, 2023. BY Italo Bruni

Nano-Ampere Area-Efficient Current Reference Based on Temperature-Controlled Pseudo-Resistor

• 2022 IEEE 13th Latin American Symposium on Circuits & Systems (LASCAS), Santiago, Chile. BY Fabián Olivera

Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node

• 28th IBERCHIP Workshop, Santiago, Chile. BY Humberto Matheus Costa Abádio 

Settling Time Modeling of the N-Stage Charge Pump Doubler Using Z Transform

• 2021 IEEE 12th Latin American Symposium on Circuits & Systems (LASCAS), Arequipa, Peru. BY Fabián Olivera

A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design (TCAS-II Invited paper)

• 2021 IEEE 12th Latin American Symposium on Circuits & Systems (LASCAS), Arequipa, Peru. BY Carlos A. Pinheiro Jr.

A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS 

• 27th IBERCHIP Workshop, Arequipa, Peru. BY Igor Meirelles Martins 

A Computer-Aided Approach for Low-Power LDO Regulator Design

• IEEE International Symposium on Circuits & Systems (2020) (CAS Transactions Papers) BY Fabián Olivera

Adjustable Output CMOS Voltage Reference Design

• IEEE International Symposium on Circuits & Systems (2020) (CAS Transactions Papers) BY Fabián Olivera

Closed-Form Analysis of Metastability Voltage in 28 nm UTBB FD-SOI CMOS Technology

• IEEE International Symposium on Circuits & Systems (2017) BY Fabián Olivera

Analytic Modeling of Static Noise Margin Considering DIBL and Body Bias Effects

• 29th Symposium on Integrated Circuits and Systems Design (2016) BY Fabián Olivera

Analytic boundaries for 6T-SRAM design in standby mode

• IEEE 6th Latin American Symposium on Circuits & Systems (2015) BY Fabián Olivera

A Computer-Aided Approach for Voltage Reference Circuit Design