- Computer Architecture Intern at Marvell (May 2019 – August 2019)
Researching and modeling new features to push the boundaries of next generation multicore high perofrmance computing systems
- CPU Architecture Intern at Intel (May 2017 – August 2017)
Studying the heterogeneity in TLB miss behavior. Proposing a design to reduce TLB misses caused by heterogonous page accesses (Patent pending. Paper to be published in ICS ‘19)
- Research Assistant (January 2016 – Present)
- Reducing cache line flush/writeback overheads incurred as a result of maintaining crash consistency in Non-Volatile Main Memory (NVMM)
- Rethinking highly-used commodity algorithms, such as Graph Breadth-First Search, in context of NVMM
- Studying algorithm-level and system-level checkpointing in NVMM: Proposing low-overhead recompute-based technique for dense matrix scientific applications (PACT ‘17)
- Teaching Assistant (August 2015 – Present)
Parallel Computer Architecture (ECE 506) - GPU Architecture (ECE 786)– Operating Systems Design (ECE 592)