Hussein Elnawawy

Annocunements

Our paper on heterogeneity in TLB-miss behavior has been accepted in ICS 2019. The paper shows that few outlier page translations cause significant number of TLB misses. It proposes a mechanism to address this disparity.
I will be working for Marvell Semiconductors from May 28th until August 16th as an intern.
My internship at Marvell has been extended until December 2019.
(31 October 2019) Just passed the Preliminary Oral Examination for my Ph.D. For the architecture folks at the ECE department in NCSU, the Prelim is THE exam. The defense is more of an honorary event. I will defend end of February (And yes, my prelim was on Halloween! The irony is irresistible!)

About me

I am a Computer Enigneering Ph.D. candidate at North Carolina State University working under Professor Greg Byrd's advisement.

My research interests are computer architecture and systems with more focus on Non-Volatile Memory (NVM), virtual memory, and heterogeneous systems.

My NVM research focuses on algorithm-level and hardware-level modifications towards integrating NVMs in modern computer systems.

This is the list of projects I work(ed) related to NVMs:

Reducing cache line flush/writeback overheads incurred as a result of maintaining crash consistency in Non-Volatile Main Memory (NVMM)
Rethinking highly-used algorithms, such as Graph Breadth-First Search, in context of NVMM
Studying algorithm-level and system-level checkpointing in NVMM: Proposing low-overhead recompute-based technique for dense matrix scientific applications

During my internship at Intel, I worked on an architecture project to address heterogeneity in TLB miss behavior. We devised and proposed a design to reduce TLB misses caused by heterogenous page accesses. The proposal is currently patent-pending.

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