Keynotes

Recent advancements have positioned Large Language Models (LLMs) as transformative tools for scientific research, capable of addressing complex tasks that require reasoning, problem-solving, and decision-making. Their exceptional capabilities suggest their potential as scientific research assistants, but also highlight the need for holistic, rigorous, and domain-specific evaluation to assess effectiveness in real-world scientific applications.

This talk describes a multifaceted methodology for Evaluating AI models as scientific Research Assistants (EAIRA)  developed at Argonne National Laboratory. This methodology incorporates four primary classes of evaluations. 1) Multiple Choice Questions to assess factual recall; 2) Open Response to evaluate advanced reasoning and problem-solving skills; 3) Lab-Style Experiments involving detailed analysis of capabilities as research assistants in controlled environments; and 4) Field-Style Experiments to capture researcher-LLM interactions at scale in a wide range of scientific domains and applications. These complementary methods enable a comprehensive analysis of LLM strengths and weaknesses with respect to their scientific knowledge, reasoning abilities, and adaptability. Recognizing the rapid pace of LLM advancements, we designed the methodology to evolve and adapt so as to ensure its continued relevance and applicability. This talk describes the current methodology's state. Although developed within a subset of scientific domains, the methodology is designed to be generalizable to a wide range of scientific domains.

The National Energy Research Scientific Computing Center (NERSC) is the U.S. Department of Energy's Office of Science mission high performance computing facility. In this talk, I will provide an overview of current initiatives at NERSC designed to equip both the center and its user community for the emerging landscape of quantum computing. I will highlight three strategic focus areas:

1. Quantum Computing Access at NERSC: This initiative provides access to classical supercomputing resources and select quantum hardware to enable cutting-edge research at the intersection of high-performance computing (HPC), quantum information science, and quantum simulation.

2. NERSC's Collaboration with QuEra Computing: Our ongoing R&D partnership explores the capabilities of neutral atom quantum hardware, aiming to accelerate breakthroughs in targeted scientific applications.

3. NERSC's Quantum Benchmarking Efforts: We are developing robust tools and methodologies to assess the performance, capabilities, and limitations of existing and future quantum computing systems.

Additionally, I will discuss NERSC's vision and roadmap for further advancing quantum computing integration into NERSC's workloads in the coming years.

With the broad rollout of AI inference capabilities, opportunities to either replace or enhance traditional DSP functionality with an AI inference function presents itself. However, most silicon and platform offerings generally have separate acceleration for DSP and AI, even though functionally both operations are very similar at the compute level. Options to recover and reuse an enhanced DSP block (i.e., a "Dense Compute Block") in an FPGA for AI inference with variable fixed point data widths are explored, with practical examples highlighted in current FPGA architectures.

NTT is advancing the IOWN (Innovative Optical and Wireless Network) initiative, a next-generation communications infrastructure, and developing a computer architecture capable of efficiently processing large volumes of advanced applications made possible by IOWN with high power efficiency. Disaggregated computing is a novel architecture that pools diverse computing resources, dynamically allocating only the necessary ones for efficient application execution.

This presentation will provide an overview of Optical Disaggregated Computing and related trends. Additionally, I will introduce Hardware Function Chaining, a technology designed to enable flexible, low-latency connections between hardware accelerators within resource pools, along with an FPGA concept implementation leveraging this technology.