Chiplet Placement and Routing Optimization: A Novel Benchmark and Neural Solver
Haeyeon Kim*, Federico Berto*, Chuanbo Hua, Minsu Kim, Joungho Kim and Jinkyoo Park (* equal contribution)
NeurIPS 2024 ML for Systems Workshop
Accelerating Chiplet Placement and Routing Optimization with Machine Learning
Haeyeon Kim*, Federico Berto*, Jounghyun Lee, Hyunjun An, Taein Shin, Chuanbo Hwa, Jinkyoo Park, Youngwoo Kim and Joungho Kim (* equal contribution)
Proceedings of DesignCon 2025. (Oral Presentation)
Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network
Haeyeon Kim, Joonsang Park, Hyunah Park, Keeyoung Son, Hyunsik Kim, Taeil Bae, Haekang Jung, and Joungho Kim
Proceedings of the IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS) 2024. (Oral Presentation)
DevFormer: A Symmetric Transformer for Context-Aware Device Placement
Haeyeon Kim*, Minsu Kim*, Federico Berto, Joungho Kim and Jinkyoo Park (* equal contribution)
Proceedings of the 40th International Conference on Machine Learning (ICML) 2023.
Learning Beyond Low-Quality Data Distribution: An Application to Optimal Decap Placement
Haeyeon Kim, Minsu Kim, Jinkyoo Park, and Joungho Kim
Proceedings of the DesignCon 2023. (Oral Presentation)
Collaborative Symmetricity Exploitation for Offline Learning of Hardware Design Solver
Haeyeon Kim*, Minsu Kim*, Joungho Kim, and Jinkyoo Park (* equal contribution)
NeurIPS 2022 Offline RL Workshop.
Imitate Expert Policy and Learn Beyond: A Practical PDN Optimizer by Imitation Learning
Haeyeon Rachel Kim, Minsu Kim, Seonguk Choi, Jihun Kim, Joonsang Park, Keeyoung Son, Hyunwook Park, Subin Kim and Joungho Kim
Proceedings of the DesignCon 2022. (Oral Presentation)
Deep Reinforcement Learning Framework for Optimal Decoupling Capacitor Placement on General PDN with an Arbitrary Probing Port
Haeyeon Kim, Hyunwook Park, Minsu Kim, Seonguk Choi, Jihun Kim, Joonsang Park, Seongguk Kim, Subin Kim,and Joungho Kim
Proceedings of the IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS) 2021.
RL4CO: a Unified Reinforcement Learning for Combinatorial Optimization
Federico Berto, Chuanbo Hua, Junyoung Park, Minsu Kim, Hyeonah Kim, Jiwoo Son, Haeyeon Kim, Joungho Kim, Jinkyoo Park
Knowledge Discovery and Data Mining (KDD) 2025. (Oral Presentation)
Large Language Models as Hyper-Heuristics for Combinatorial Optimization
Haoran Ye, Jiarui Wang, Zhiguang Cao, Federico Berto, Chuanbo Hua, Haeyeon Kim, Jinkyoo Park, Guojie Song
Proceedings of the 38th Neural Information Processing Systems (NeurIPS) 2024.
[23] Jihun Kim, Seonguk Choi, Taein Shin, Keeyoung Son, Boogyo Sim, Seongguk Kim, Haeyeon Kim, Joonsang Park,
Jinwook Song, Kyungsuk Kim, Jonggyu Park and Joungho Kim, "Imitation Learning-based Equalizer Design Optimization Method on PCIe 6.0.," in Proceedings of the 2023 IEEE Electrical Design of Advanced Packaging and Systems,
[22] Seongguk Kim, Keeyoung Son, Jiwon Yoon, Taein Shin, Keunwoo kim, Boogyo Sim, Hyunwook Park, Joonsang Park, Seonguk Cho, Jihun Kim, Haeyeon Kim and Joungho Kim, "Signal Integrity Analysis of High-speed PCIe Channel with Board-to-Board Interconnect for High-Performance Server," in Proceedings of the 2023 IEEE Electrical Design of Advanced Packaging and Systems,
[21] Hyunwoo Kim, Seonguk Choi, Joonsang Park, Haeyeon Kim, Keeyoung Son, Junghyun Lee, Jiwon Yoon, Jonghyun Hong, Boogyo Sim, Keunwoo Kim, Taein Shin, and Joungho Kim, "Modeling and Analysis of Simultaneous Switching Noise for Full Wafer Scale Chip Core," in Proceedings of the 2023 IEEE Electrical Performance of Electronic Packaging and Systems,
[20] Juneyoung Kim, Seonguk Choi, Seongguk Kim, Jihun Kim, Boogyo Sim, Junghyun Lee, Taein Shin,
Hyunwoo Kim, Jonghyun Hong, Haeyeon Kim, Joonsang Park , and Joungho Kim, "Crosstalk Mitigated On-chip Interconnect Design for High-speed Network-on-Chip (NoC) of Full Wafer Scale Chip (FWSC)," in Proceedings of the 2023 IEEE Electrical Performance of Electronic Packaging and Systems,
[19] Joonsang Park, Seongguk Kim, Keeyoung Son, Haeyeon Kim, Hyunwoo Kim, Hyunsik Kim, Seonguk Choi, Jihun Kim, and Joungho Kim, "Design and Analysis of an Irregular-Shaped Power Distribution Network (PDN) for High Bandwidth Memory (HBM) Interposer," in Proceedings of the 2023 IEEE Electrical Performance of Electronic Packaging and Systems,
[18] Hyunah Park, Haeyeon Kim, Hyunwoo Kim, Joonsang Park, Seonguk Choi, Jihun Kim, Keeyoung Son, Haeseok Suh, Taesoo Kim, Jungmin Ahn and Joungho Kim, "Versatile Genetic Algorithm-Bayesian Optimization(GA-BO) Bi-Level Optimization for Decoupling Capacitor Placement," in Proceedings of the 2023 IEEE Electrical Performance of Electronic Packaging and Systems,
[17] Boogyo Sim, Taein Shin, Hyunwook Park, Keeyoung Son, Keunwoo Kim, Daehwan Lho, Hyungmin Kang, Joonsang Park, Haeyeon Kim, Jihun Kim, Seonguk Choi and Joungho Kim, "Bayesian Optimization based Fast and Accurate Wireless Power Transfer System Coil Optimization for High Efficiency ," in Proceedings of the 2023 IEEE Wireless Power Technology Conference and Expo ,
[16] Seonguk Choi, Jihun Kim, Minsu Kim, Hyunwook Park, Haeyeon Kim, Joonsang Park, Keeyoung Son, Seongguk Kim, Taein Shin, Keunwoo Kim, Jiwon Yoon, Jinwook Song, Kyungsuk Kim, Jonggyu Park, and Joungho Kim, "Extremely Fast Dynamic Link Equalization for PCIe based on Imitation Learning," in Proceedings of the 2023 DesignCon,
[15] Hyunwoo Kim, Haeyeon Kim, Joonsang Park, Keeyoung Son, Hyunwook Park, Taein Shin, Keunwoo Kim, Jiwon Yoon, Junghyun Lee, Jonghyun Hong, Juneyoung Kim and Joungho Kim, "Design and Analysis of Hierarchical Power Distribution Network (PDN) for Full Wafer Scale Chip (FWSC) Module," in Proceedings of the 2022 IEEE Electrical Design of Advanced Packaging and Systems,
[14] Keeyoung Son, Daehwan Lho, Keunwoo Kim, Seonguk Choi, Haeyeon Kim, Hyunwook Park, Boogyo Sim, Hyunwoo Kim, Taein Shin and Joungho Kim, "Power Distribution Network Impedance Analysis considering Thermal Distribution," in Proceedings of the 2022 IEEE Electrical Design of Advanced Packaging and Systems,
[13] Kyungjune Son, Keunwoo Kim, Gapyeol Park, Daehwan Lho, Hyunwook Park, Boogyo Sim, Taein Shin, Joonsang Park, Haeyeon Kim, Kyubong Gong and Joungho Kim, "Signal Integrity and Power Leakage Optimization for 3D X-Point Memory Operation using Reinforcement Learning," in Proceedings of the 2022 IEEE Electrical Performance of Electronic Packaging and Systems.
[12] Daehwan Lho, Hyunwook Park, Keunwoo Kim, Seongguk Kim, Boogyo Sim, Kyungjune Son, Keeyoung Son, Jihun Kim, Seonguk Choi, Joonsang Park, Haeyeon Kim, Kyubong Kong and Joungho Kim, "Deterministic Policy Gradient-based Reinforcement Learning for DDR5 Memory Signaling Architecture Optimization considering Signal Integrity," in Proceedings of the 2022 IEEE Electrical Performance of Electronic Packaging and Systems.
[11] Keeyoung Son, Seongguk Kim, Keunwoo Kim, Hyunwook Park, Minsu Kim, Taein Shin, Seonguk Choi, Joonsang Park, Jihun Kim, Haeyeon Rachel Kim and Joungho Kim, "Thermal Transmission Line: Smoothing Thermal Gradients and Lowering Temperature for Signal Integrity Improvement of HBM and 2.5D ICs," in Proceedings of the 2022 DesignCon.
[10] Seonguk Choi, Minsu Kim, Hyunwook Park, Haeyeon Kim, Joonsang Park, Jihun Kim, Keeyoung Son, Seongguk Kim, Keunwoo Kim, Daehwan Lho, Jiwon Yoon, Jinwook Song, Kyungsuk Kim, Jonggyu Park and Joungho Kim, "Deep Reinforcement Learning-based Channel-flexible Equalization Scheme: An Application to High Bandwidth Memory," in Proceedings of the 2022 DesignCon.
[9] Joonsang Park, Minsu Kim, Seonguk Choi, Jihun Kim, Haeyeon Kim, Hyunwook Park, Seongguk Kim, Taein Shin and Joungho Kim, "Learning Super-scale Microbump Pin Assignment Optimization for Real-world PCB Design with Graph Representation," in Proceedings of the 2022 DesignCon.
[8] Jihun Kim, Minsu Kim, Hyunwook Park, Jiwon Yoon, Seonguk Choi, Joonsang Park, Haeyeon Kim, Keeyoung Son, Seongguk Kim, Daehwan Lho, Keunwoo Kim, Jinwook Song, Kyungsuk Kim, Jonggyu Park and Joungho Kim, "Imitation Learning with Bayesian Exploration (IL-BE) for Signal Integrity (SI) of PAM-4 based High-speed Serial Link: PCIe 6.0," in Proceedings of the 2022 DesignCon.
[7] Seongguk Kim, Taein Shin, Hyunwook Park, Daehwan Lho, Keeyoung Son, Keunwoo Kim, Joonsang Park, Seonguk Choi, Jihun Kim, Haeyeon Kim, and Joungho Kim., "Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM)," 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2021, pp. 1-3, doi: 10.1109/EDAPS53774.2021.9657033.
[6] Jihun Kim, Hyunwook Park, Minsu Kim, Seongguk Kim, Seonguk Choi, Keeyoung Son, Joonsang Park, Haeyeon Kim, Jinwook Song, Youngmin Ku, Jonggyu Park, and Joungho Kim., "PAM-4 based PCIe 6.0 Channel Design Optimization Method using Bayesian Optimization," 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3, doi: 10.1109/EPEPS51341.2021.9609213.
[5] Seonguk Choi, Minsu Kim, Hyunwook Park, Keeyoung Son, Seongguk Kim, Jihun Kim, Joonsang Park, Haeyeon Kim, Taein Shin, Keunwoo Kim, and Joungho Kim., "Sequential Policy Network-based Optimal Passive Equalizer Design for an Arbitrary Channel of High Bandwidth Memory using Advantage Actor Critic," 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3, doi: 10.1109/EPEPS51341.2021.9609193.
[4] Joonsang Park, Minsu Kim, Seongguk Kim, Keeyoung Son, Taein Shin, Hyunwook Park, Jihun Kim, Seonguk Choi, Haeyeon Kim, Keunwoo Kim, and Joungho Kim., "Deep Reinforcement Learning-based Pin Assignment Optimization of BGA Packages considering Signal Integrity with Graph Representation," 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3, doi: 10.1109/EPEPS51341.2021.9609139.
[3] Minsu Kim, Hyunwook Park, Keeyoung Son, Seongguk Kim, Haeyeon Kim, Jihun Kim, Jinwook Song, Youngmin Ku, Jonggyu Park, and Joungho Kim., "Imitation Learning for Simultaneous Escape Routing," 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3, doi: 10.1109/EPEPS51341.2021.9609145.
[2] Minsu Kim, Hyunwook Park,Seonguk Choi, Haeyeon Rachel Kim, Seongguk Kim,Keeyoung Son,Keunwoo Kim,Daehwan Lho,Kyunjune Son,Subin Kim, and Joungho Kim, "Neural Language Model Enables Extremely Fast and Robust Routing on Interposer," in Proceedings of the DesignCon 2021.
[1] Subin Kim, Seungtaek Jeong, Boogyo Sim, Seongsoo Lee, Hyunwook Park, Haeyeon Kim, and Joungho Kim.,"Design and Analysis of On-package Inductor of an Integrated Voltage Regulator for High-Q Factor and EMI Shielding in Active Interposer based 2.5D/3D ICs," 2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium, 2021, pp. 498-503, doi: 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559188.