HAEYEON RACHEL KIM

Hello, I'm Haeyeon Rachel Kim, a Ph.D. candidate in electrical engineering at KAIST, South Korea, advised by Professor Joungho Kim at the Terabyte Interconnection and Package Laboratory (TERA Lab).

My research focuses on addressing power integrity and signal integrity issues in 2.5D and 3D integrated circuits (ICs), with a particular emphasis on optimizing power distribution networks for 2.5D High Bandwidth Memory (HBM) modules. These hardware design problems are often simulation-intensive and NP-hard, making them challenging to solve using traditional methods. To tackle these complex challenges, I implement machine learning and reinforcement learning techniques, driven by my deep interest in hardware design automation.

At TERA Lab, I collaborate with talented researchers on cutting-edge projects, exploring innovative approaches to streamline the design process and enhance the performance of advanced packaging technologies. By leveraging the power of machine learning, I strive to develop efficient and intelligent solutions that can handle the simulation-intensive and NP-hard nature of these problems.

I am excited about the potential impact of my research on the future of 2.5D and 3D IC design and its applications in various domains. As I progress in my Ph.D. journey, I am eager to push the boundaries of power integrity and signal integrity optimization, shaping the future of hardware design automation through the application of advanced algorithms and techniques.