Cardiac Monitoring System Design Process

1. First, we started by creating truth tables and logic equations to define the behavior of our cardiac monitoring system. We mapped out all possible combinations of the three inputs and determined the corresponding outputs. We used Boolean algebra to simplify our logic equations and decided that we would use a combination of AND gates, OR gates, and inverters to implement our decision for the four alert levels.
   
   

2. Secondly, we divided our team into specialized groups to work on different components of the project simultaneously. We assigned team members based on their strengths: some focused on the research paper and documentation, others worked on the 555 timer circuit design, another group tackled the alarm system implementation, and the remaining members concentrated on building and testing the logic circuits using 7408, 7432, and 7404 chips.
   
   

3. Thirdly, we began constructing the 555 timer circuit to provide the system's heartbeat and monitoring intervals. We designed the circuit to operate in astable mode to generate regular clock pulses for checking patient indicators. We used breadboards initially to test our timing calculations and ensure stable operation before moving to the final circuit board.
   
   

4. Fourthly, we implemented the digital logic circuits using discrete logic gates to process the three cardiac indicator inputs. We built the combinational logic using 7408 AND gates to detect multiple simultaneous risk factors, 7432 OR gates to trigger alerts when any indicator was present, and 7404 inverters for signal conditioning. We also incorporated 74374 D flip-flops to store patient states and prevent the system from forgetting critical events, ensuring proper medical documentation and alert persistence.
   
   

5. Fifthly, we constructed and tested the alarm system that provides visual and audible feedback based on the logic circuit outputs. We integrated LED indicators for the different alert levels (green for normal, yellow for single risk factor, red for dual factors) and implemented a buzzer system for the emergencies listed when all three indicators are present. We found several issues during initial testing including incorrect wiring connections and  improper use of circuits
   
   

6. Sixthly, we troubleshot these problems through systematic debugging and the help of Mr Irvine to consult on our cicruit design. We discovered that our initial capacitor values in the 555 timer were too small, causing unstable operation, so we replaced them with higher-capacity components. We also had to rewire several connections on our breadboard after discovering crossed signals between the logic gates. We tested each subsystem individually before integrating them together, which helped us isolate problems and verify that each component functioned correctly before final assembly.
   
   

7. Finally, we integrated all components into a complete monitoring system and conducted comprehensive testing to verify proper operation across all alert levels. We simulated various combinations of cardiac indicators. While our final prototype was not succxesful we still managed to demonstrated the core monitoring functionality, we identified areas for improvement including better wire management, more robust power supply design, and enhanced signal filtering to reduce noise in the logic circuits.
   
   

Circuits Used:

555 Timer Circuit:

The 555 timer in astable mode generates a timed pulse signal that acts as a clock input for triggering alerts and synchronizing output behavior in the alarm system.

Alarm Circuit:
The alarm circuit integrates logic gates and outputs to activate a buzzer and LED indicators when critical health conditions are detected from multiple input signals.

D Flip-Flop Circuit:

The D flip-flop circuit stores and stabilizes input logic states based on the timer’s clock signal, ensuring that changes in sensor inputs are reliably captured and translated into system actions.

Logic:

AND gates (7408): Triggered outputs when multiple critical inputs were present.

OR gates (7432): Allowed any single indicator to initiate a response.

NOT gates (7404): Inverted logic levels where needed for correct output behavior.