Network architectures, topology
Hardware (FPGA/ASIC) based scheduling-control for circuit switched & packet switched networks
Memory disaggregation; Remote memory transaction protocols; Optical network and data center architecture; Compute and network resource allocation; FPGA/MPSoC systems; Remote memory transaction protocols
Multi-dimensional (space-wavelength) resource allocation
Testbeds and experiments on ultrafast space and wavelength switching/tuning.
Multi-core fibre switch design and experimentation
AI-based weakly coupled MCF design, MCF characterization and crosstalk modelling
AI based MCF transceiver optimization
MCF based networks
Routing, Spectrum, Core, and Modulation allocation allocation
Open/White-Box/Disaggregated versus Black-Box/Integrated Optical Node/Networking
Hardware programmable network function service chain
... more information upon request
Matlab based simulator (verified with SystemVerilog) that explores optical circuit switching based to hardware scheduler for time-slot and wavelength allocation.
SystemVerilog based emulator for investigating data (buffering, switching) architectures such as Clos and Crossbar and critically hardware based packet scheduling and control plane functionality.
A tool has been developed to design homogeneous and heterogeneous weakly coupled multi-core fibers.
Traffic generator to stress test networks and computing systems (resource/job scheduling algorithms, topologies, protocols, switches). Trafpy generates either flow distributions or a computation graph, job distributions, whose dependencies (edges) may form flows. Both flow-centric and job-centric network demand generation and management are supported by TrafPy.
A tool and source code is available that used genetic algorithm, particle swarm optimization, and ant colony optimization to generate multi-level drive signals to calibrate/optimize the on-off (switching) function (settling time) of any semiconductor optical amplifier.