RV32I SoC on a Basys 3

pong_video.mp4

Overview

A 32-bit RISC-V (RV32I) CPU in SystemVerilog with a classic five-stage pipeline, built following the design in Computer Organization and Design, RISC-V Edition: The Hardware/Software Interface (Patterson & Hennessy). It runs on a Digilent Basys 3 (Artix-7), boots compiled C over UART, drives a 640x480 VGA display, and plays Pong on real hardware. I also wrote a small UVM testbench to check the data cache on some basic cases.

Design

Five-stage pipeline with forwarding, branch prediction, and separate instruction and data caches. Runs on a Basys 3 (Artix-7) at 100 MHz, boots compiled C over UART, and drives a 640x480 VGA display. RV32I only — no multiply/divide extension and no traps yet.

Verification & Results

Since a CPU that runs one game isn't necessarily correct, I spent a fair amount of time on verification. I built a small UVM testbench in Vivado XSim for the data cache, plus directed CPU tests and self-checking C programs that run on the board. This turned up a few real bugs, including a forwarding bug that only showed up when the data cache stalled the pipeline.

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